參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 46/72頁(yè)
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external memory interface (continued)
External Memory
Interface (EMIF)
E
E
H
H
S
S
S
S
S
S
S
S
S
A
A
A
X
Synchronous
DRAM
C
B
Synchronous
Burst SRAM
Async Mem,
External Cntrl
External
Control
Figure 28. External Memory Interface
asynchronous memory cycles
Asynchronous memory read cycles use the AXOE control signal to enable the memory device to place the data
on the data bus. EMIF CE-space timing registers define the shape of the read cycle and the amount of time that
each address is valid. The shape of the read cycle in Figure 29, reflects the fastest possible asynchronous read
corresponding to one-cycle setup, one-cycle strobe width, and one-cycle hold fields of the EMIF CE space
timing register.
Asynchronous memory write cycles use the AXWE control signal to latch the data in the memory device. The
AXWE signal shape is programmed by setting fields in the EMIF CE-space timing register. The cycles in
Figure 30 correspond to one-cycle set up, one-cycle strobe width, and one-cycle hold time (fastest write
possible). Asynchronous memory AXOE and AXWE control signals are also used during external control cycles.
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Set-up time, read D before CLKOUT1 high
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switching characteristics for asynchronous memory cycles
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1
2
Delay time, CLKOUT1 high to BE valid
3
td(CKH-A)
Delay time, CLKOUT1 high to EA valid
4
td(CKH-D)
Delay time, CLKOUT1 high to ED valid
td(CKH-WE)
Delay time, CLKOUT1 high to AXWE valid
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Delay time, CLKOUT1 high to CE valid
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PARAMETER
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CONDITIONS
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UNIT
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1.7
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