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參數(shù)資料
| 型號(hào)： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器） |
| 文件頁(yè)數(shù)： | 2/72頁(yè) |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description
The TMX320C6201 fixed-point DSP is based on the VelociTI
VLIW ’C6200 CPU core. It executes up to eight
instructions every clock cycle to achieve 1600 MIPS performance at 200 MHz. Eight functional units operate
in parallel using two register files with 16 32-bit registers each. Program parallelism is defined at compile time
to remove the need for hardware control of data interlocking. The 1M-bit on-chip RAM is split between data and
program memory. The 256-bit-wide program memory fetches eight 32-bit instructions every single cycle. The
program memory also can be configured as cache memory. The external memory interface (EMIF) supports
a variety of synchronous and asynchronous memories including SBSRAM and SDRAM. EMIF can release the
external bus under host control using hold/hold-acknowledge protocol. Additionally, the host has a direct
access to the processor data memory by way of the separate 16-bit host-port interface. Following power up,
the ‘C6201 can be booted from 8-, 16- or 32-bit external ROM using one of the two direct memory access (DMA)
channels available on the chip. See the functional block diagram for a high-level functional diagram of the
TMX320C6201. Dashed lines highlight features that are to be added in the next release (including serial ports
and timers).
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