參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 20/72頁(yè)
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
internal memory
The internal memory consists of 512K bits of on-chip program/cache memory and 512K bits of on-chip data
memory. The program memory, configurable as cache or program, is organized in 2K of 256-bit fetch packets.
The ’C6201 fetches all instructions one fetch packet at a time. The packets are processed at the maximum rate
of one packet (eight 32-bit instructions) per CPU cycle or at a minimum of one instruction per cycle. The internal
data memory is byte addressable by the CPU (for reads as well as writes) and supports bytes, half-words, and
full word transfers.
external memory
All external data accessed by the CPU or DMA pass through the external memory interface (EMIF). The external
memory is divided into three spaces: CE0, CE1, and CE2. Each has a dedicated chip-enable signal that is
asserted during data access to or from the corresponding space. Each external space has assigned a separate
internal peripheral bus register (CE space timing register) that determines the shape of the read/write cycle for
the particular space when accessing asynchronous memory.
In addition to asynchronous memory, CE0 and CE2 spaces also can interface to other types of memory.
SBSRAM or SDRAM memory can be assigned to those two spaces by controlling signal levels on signal groups
CE0_TYPE and CE2_TYPE (pins DC2–DC5) during reset.
External memory space CE1 can interface only to asynchronous memory. While spaces CE0 and CE1 are
always 32-bits wide, the CE1 memory space also can be configured to a memory width of 8 or 16 bits by
controlling signal levels on HPI pin MEM_CE1.The flexibility of the EMIF to pack bytes and half-words
automatically into words during read cycles becomes especially convenient when booting from an 8- or 16-bit
EPROM. The CE1 memory space can be used for ROM interfacing because ROM cycles are identical to
asynchronous SRAM read cycles.
The CE1 space is the only external-memory space that allows read cycles from 8- or 16-bit-wide memory, but
read cycles from any external-memory space can access byte or half-word-sized data from 32-bit-wide external
memory. The EMIF data-write cycles can transfer bytes, half-words, or words to external memory as well, using
BE control signals for byte selects. Data-read cycles always latch all 4 bytes (all 4 BEs active) and the CPU then
extracts the appropriate bytes internally if the data size is less 32 bits. The EMIF writes requested by the
program-memory controller or the DMA are always 32 bits wide (as opposed to 8-, 16-, or 32-bit transfers
originated by the data-memory controller).
The state of pin DC1 (MAP_BOOT signal group) during reset determines whether the internal-program RAM
is placed in the memory map before or after the external memory spaces CE0 and CE1. The type of memory
map mode chosen typically depends on the startup procedure used following the device power up (see the
startup following resetsection.
The endian-configuration pin (LENDIAN) determines the order in which the individual byte addresses increase
within the word (the low byte within a word can represent bits 0–7 or bits 24–31of the 32-bit word). In the
analogous way, the endian pin also determines the order of half-words within the word. The LENDIAN pin affects
the internal-data memory as well as external-memory accesses.
internal peripherals
The peripherals on the ’C6x are accessed and controlled through memory-mapped control registers. The
TMX320C6201 features two peripherals — the external memory interface (EMIF) and the two-channel direct
memory access controller (DMA). One of the DMA channels, DMA0, is used by the processor during the boot
load start-up procedure to initialize the internal-program memory after reset. Figure 6 shows the registers.
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