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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 52/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
synchronous burst SRAM (SBSRAM) cycles
Figure 34 and Figure 35 show read and write cycles transferring data between the ’320C6201 DSP and
SBSRAM. The SBSRAM interface consists of four dedicated SBSRAM control signals. The address strobe,
SSADS, is used to latch the first address of the burst into the SBSRAM device. For a write cycle, it is asserted
continuously as long as data is being transferred. For read cycles, the SSADS signal is asserted only for the
first word of the burst transfer and each time the address breaks the sequence. The burst size (1 to 4 reads)
is determined by the two lowest order bits of the address (EA1 and EA0). Once the read address is latched in
the SBSRAM, the ’320C6201 DSP asserts the address advance signal and keeps it low as long as the desired
address is the next address in sequence. The SSOE signal allows the SBSRAM device to place the data on
the bus, while the SSWE enables the SBSRAM to receive data.
timing requirements for synchronous burst SRAM (SBSRAM) cycles
NO
MIN
MAX
UNIT
5
tsu(D-CKH)
th(CKH-D)
Setup time, read ED before CLKOUT1 high
0.5
ns
6
Hold time, read ED valid after CLKOUT1 high
2.0
ns
switching characteristics for synchronous burst SRAM (SBSRAM) cycles (see Note 3)
NO
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1
td(CKH-CE)
td(CKH-BE)
td(CKH-A)
td(CKH-D)
td(CKH-ADS)
td(CKH-ADV)
td(CKH-SSOE)
td(CKH-SSWE)
Delay time, CLKOUT1 high to CE valid
1.9
ns
2
Delay time, CLKOUT1 high to BE valid
2.2
ns
3
Delay time, CLKOUT1 high to EA valid
0
0
1.7
ns
4
Delay time, CLKOUT1 high to ED valid
2.0
ns
7
Delay time, CLKOUT1 high to SSADS valid
1.5
ns
8
Delay time, CLKOUT1 high to SSADV valid
1.8
ns
9
Delay time, CLKOUT1 high to SSOE valid
2.1
ns
10
Delay time, CLKOUT1 high to SSWE valid
2.0
ns
Values specified by design and not tested
NOTE 3: The SSADS signal is pulsed each time the address crosses the modulo 4 boundary (EA0 and EA1 are 0) and during the first access
at the beginning of a burst (see Figure 34).
P
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