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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 29/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
boot-loader start up (continued)
8-bit
EPROM
0140 0000h
CPU
DMA
Transfer
Internal
Program
Memory
0000 0000h
Instr
Fetch
DMA0
DMA0 Boot
Transfer
Count = 1024
Words
Low to High
Transition
3.3 V
3.3 V
GND
GND
RESET
DC1 (Memory Map 1)
DC11 (Boot-Load Start Up)
DC12 (Boot-Load Start Up)
DC13 (Boot-Load Start Up)
DC10
DC9
DC8
DC7
DC6
GND
3.3 V
GND
GND
GND
CE1 Space
Memory Width
= 8 Bits
1
2
Figure 14. Boot-Load Start-Up Mode After Reset
interrupt servicing
Before an interrupt can be processed automatically, its corresponding bit must be set in the interrupt-enable
register. the IER NMIE bit must be set and the global-interrupt-enable bit (GIE) must be set as well in the control
status register (CSR). During interrupt processing, the processor stops current program execution and saves
the address of the next instruction scheduled for execution in the Interrupt-return pointer (IRP). In the case of
the non-maskable interrupt (NMI), the return address is saved in the NRP register. Program execution is then
redirected to one of 16 pre-assigned contiguous locations in the interrupt service table (IST) The IST base is
assigned to address 0h following reset, but can be relocated anywhere on a 1K-byte address boundary by
changing the ISTB field of the ISTP register). The ISFPs consist of eight instructions of which one has to be a
branch to the the IRP address (to return from interrupt) or a branch to additional code if the interrupt service
routine (ISR) is larger then the ISFP (see Figure 15). The branch must be executed at least five cycles before
the end of the ISFP to prevent intrusion into ISFPs belonging to other interrupts. This can be accomplished either
by placing the branch five non-parallel instructions before the end of the ISFP or by following the branch with
a NOP 5instruction.
With the GIE bit disabled, the highest priority active interrupt still can be identified in software by polling the ISTP
register containing the address pointing to the ISFP of the next interrupt in line for processing if the GIE were
enabled. All active interrupts also can be identified by polling the interrupt flag register (IFR). Interrupt set and
clear registers (ISR and ICR) can be used to set/clear interrupts manually in software.
During automatic-interrupt processing, the IFR bit is cleared, and the active interrupt is encoded on the four
INUM pins, at the beginning of the IACK pulse (see the timing sectionof the data sheet). At the same time, the
GIE bit is copied to the PGIE field of CSR, and the GIE bit is cleared for all interrupts except NMI. The PGIE
bit is copied back to GIE field upon return from interrupt through the B IRPinstruction (at the end of the E1
phase). Returning from NMI interrupt by the way of the B NRPinstruction does not copy the PGIE bit to the GIE
field.
P
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