參數資料
型號： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP)
中文描述： 數字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數字信號處理器）
文件頁數： 49/72頁
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
asynchronous memory cycles
The CE space timing register contains three fields that determine the shape and duration of the AXWE and
AXOE control signals. The examples shown in Figure 29 and Figure 30 correspond to value of 1 programmed
in set-up, strobe, and hold fields of the CE space timing register (the smallest value permitted). Each read and
write also contains a one-cycle internal address latch time which is not programmable. Even as the AXOE signal
does not come up in between the successive read cycles, the combined effect of set-up, strobe, and hold values
determines the total length of each read (see Figure 31).
CE Space
Ti i
Timing
Register
31 20
19 16
SETUP
15 14
13 8
STROBE
7 2
1 0
HOLD
RSV
RSV
RSV
Reserved
Set-up time
before strobe
falling edge
Reserved
Active strobe
width
Reserved
Hold time
after strobe rising
edge
The smallest value permitted for this field is 1.
Figure 31. CE Space Timing Register
external controller cycles
Any external memory access in CE space 0 and 2 can be converted to an external controller cycle by setting
appropriate bits in the EMIF global control register. All external controller cycles use AXOE and AXWE control
signals to specify the direction of data transfer. For both reads and writes, the ’320C6201 DSP drives the XREQ
control signal low to announce the start of a read or write cycle. If the external device is ready for the data
transfer, it immediately drives the AXRDY signal high. AXRDY remains high as long as the external device is
ready to transfer data. When the external device is not ready to transfer, it immediately brings the AXRDY line
low to stall the current bus cycle until it is ready again. See Figure 32 and Figure 33 for timing waveforms.
timing requirements for external controller cycles
NO
MIN
MAX
UNIT
5
tsu(D-CKH)
th(CKH-D)
td(CKH-XREQ)
Setup time, read ED before CLKOUT1 high
1.0
ns
6
Hold time, read ED valid after CLKOUT1 high
2.0
ns
9
Delay time, CLKOUT1 high to XREQ valid
1.3
ns
switching characteristics for external controller cycles
NO
PARAMETER
MIN
MAX
UNIT
1
td(CKH-CE)
td(CKH-BE)
td(CKH-A)
td(CKH-D)
td(CKH-OE)
td(CKH-WE)
tsu(XRDY-CKH)
th(CKH-XRDY)
Delay time, CLKOUT1 high to CE valid
1.9
ns
2
Delay time, CLKOUT1 high to BE valid
2.2
ns
3
Delay time, CLKOUT1 high to EA valid
0
0
1.7
ns
4
Delay time, CLKOUT1 high to ED valid
2.0
ns
7
Delay time, CLKOUT1 high to AXOE valid
1.9
ns
8
Delay time, CLKOUT1 high to AXWE valid
2.0
ns
10
Setup time, read XRDY valid before CLKOUT1 high
0.5
ns
11
Hold time, read XRDY valid after CLKOUT1 high
2.8
ns
Values specified by design and not tested
P
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