參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 1/72頁(yè)
文件大小： 1552K
代理商： TMX320C6201
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Highest Performance Fixed-Point Digital
Signal Processor (DSP):
– 1600 MIPS @ 200 MHz
– Five-ns Cycle Time
– Eight
×
32-Bit Instructions/Cycle
VelociTI
Advanced Very-Long Instruction
Word (VLIW) Architecture:
– Eight Independent Functional Units
– Two 16-Bit Multipliers (32-Bit Results)
– Six Arithmetic Logic Units (ALUs)
(32-/40-Bit)
– Load/Store Architecture:
32 32-Bit General-Purpose Registers
– Instruction Packing to Reduce Code Size
– 100% Conditional Instructions
Instruction Set Features
– Byte-Addressable 8-, 16-, 32-Bit Data
– 32-Bit Address Range
– Dual-Endian Support
– 8-Bit Headroom Available
– Saturation
– Bit-Field Extract, Set, Clear
– Bit Counting
– Normalization
– Register or 5-Bit Constant Index
– 15-Bit Positive/Negative Offset From
Either B14 or B15 Register
1M-Bit On-Chip SRAM
– 512K-Bit Internal-Program/Cache
Memory
– 512K-Bit Internal-Data Memory
32-Bit External Memory Interface (EMIF)
– Glueless Interface To Synchronous
Memories:
Synchronous Dynamic Random-Access
Memory (SDRAM)
Synchronous Burst Static RAM
(SBSRAM)
– Glueless Interface to Asynchronous
Memories:
Static RAM (SRAM)
Erasable Programmable Read-Only
Memory (EPROM)
– Glueless Interface to External Controller
Devices:
First-In/First-Out (FIFO)
Two-Channel Boot-Loading Direct Memory
Access (DMA) Coprocessor
16-Bit Host-Access Port
Flexible Phase-Locked Loop (PLL) Clock
Generator (
×
1,
×
2,
×
4)
IEEE Std. 1149.1 (JTAG
) Scan-Based
Emulation
352-Pin Ball Grid Array (BGA) Package
0.25 micron / Five-Level Metal Process
0
°
C–90
°
C Operating Case Temperature
Range
P
Copyright
1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
VelociTI is a trademark of Texas Instruments.
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26
GGP 352-PIN BGA PACKAGE
(BOTTOM VIEW)
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