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參數(shù)資料
| 型號(hào)： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器） |
| 文件頁(yè)數(shù)： | 16/72頁(yè) |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CPU registers (continued)
31
26
25
21
20
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AMR
rsv
BK1
BK0
B7m
B6m
B5m
B4m
A7m
A6m
A5m
A4m
Reserved
Block Size 1
Block Size 0
Linear- or Circular-Addressing Mode Select
31
24
23
16
15
10
9
8
7
5
4
2
1
0
CSR
CPU ID
REVISION ID
PWRD
SAT
EN
PCC
DCC
PGIE
GIE
CPU Type
Identification
Silicon
identification
Power-Down
Modes
Saturate
Status
Endian
Control
Program/Cache
Control
Data/Cache
Control
Previous
GIE State
Global-
Interrupt
Enable
Not used on TMX320C6201 (reserved)
31
0
PCE1
Program counter (address of fetch packet containing execute packet in the E1 pipeline stage)
IN
General-purpose input (reflects status of 32 general-purpose input pins)
OUT
General-purpose output (drives 32 general-purpose output pins)
PDATA_O
Program data out (contains 32 bits used by the STP instruction to write to program space)
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IER
Reserved
IE15
IE14
IE13
IE12
IE11
IE10
IE9
IE8
IE7
IE6
IE5
IE4
rsv
rsv
NMIE
0
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IFR
Reserved
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
rsv
rsv
NMIF
0
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISR
Reserved
IS15
IS14
IS13
IS12
IS11
IS10
IS9
IS8
IS7
IS6
IS5
IS4
rsv
rsv
rsv
rsv
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICR
Reserved
IC15
IC14
IC13
IC12
IC11
IC10
IC9
IC8
IC7
IC6
IC5
IC4
rsv
rsv
rsv
rsv
31
10
9
5
4
3
2
1
0
ISTP
ISTB
HPENT
0
0
0
0
0
Interrupt-Service
Table Base
Highest Priority
IE-Enabled Interrupt
Interrupt-Service Packet Size
Address of the interrupt service fetch packet (ISFP) for the highest priority pending interrupt
31
0
IRP
Interrupt Return Address
31
0
NRP
Non-maskable Interrupt Return Address
NOTE A: Only 0s can be written to reserved fields of the registers.
Figure 3. Control Register Usage
P
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