參數(shù)資料
型號： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP)
中文描述： 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器）
文件頁數(shù)： 26/72頁
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
simultaneous internal memory access from both sides of the CPU
To visualize maximum memory-access performance, the internal data memory of the 320C6201 can be
organized in four blocks, each 2 bytes wide and 16K rows tall. As shown in Figure 10 and Figure 11, the data
is byte-addressable by the CPU with address increasing across the blocks from left to right (this example uses
little-endian mode). For both sides of the CPU to access data simultaneously during the same CPU cycle, none
of the bytes of side A data can reside in the same memory block as any of the side B data bytes. As shown in
Figure 10, a word of data is loaded to a side A register at the same time as another word is stored from a side
B register. The two accesses in Figure 11 (both 8 bits wide), however, take two cycles because both bytes reside
in the same block of the internal data memory.
8000 0000
8000 0008
8000 0001
8000 0009
8000 FFF0
8000 FFF8
8000 FFF1
8000 FFF9
8
8
8000 0002
8000 000A
8000 0003
8000 000B
8000 FFF2
8000 FFFA
8000 FFF3
8000 FFFB
8
8
8000 0004
8000 000C
8000 0005
8000 000D
8000 FFF4
8000 FFFC
8000 FFF5
8000 FFFD
8
8
8000 0006
8000 000E
8000 0007
8000 000F
8000 FFF6
8000 FFFE
8000 FFF7
8000 FFFF
8
8
32
32
CPU SIDE A
Data-Memory
Controller
CPU SIDE B
Figure 10. Simultaneous Internal Memory Access
8000 0000
8000 0008
8000 0001
8000 0009
8000 FFF0
8000 FFF8
8000 FFF1
8000 FFF9
8000 0002
8000 000A
8000 0003
8000 000B
8000 FFF2
8000 FFFA
8000 FFF3
8000 FFFB
8
8
8000 0004
8000 000C
8000 0005
8000 000D
8000 FFF4
8000 FFFC
8000 FFF5
8000 FFFD
8000 0006
8000 000E
8000 0007
8000 000F
8000 FFF6
8000 FFFE
8000 FFF7
8000 FFFF
8
8
CPU SIDE A
Data-Memory
Controller
CPU SIDE B
Figure 11. Two-Cycle Internal Memory Access
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