參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁數(shù)： 4/72頁
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
signal description
The signals in this section are organized in six groups — clock/PLL, IEEE Std. 1149.1 test access port (TAP)
emulation, control, host-port interface (HPI), external memory interface (EMIF), and voltage supply/ground.
Terminal Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
CLOCK / PLL
CLKIN
C10
I
Clock Input
CLKOUT1
AD17
O
Clock output at full device speed (can be used as input to SBSRAM)
CLKOUT2
AE20
O
Clock output at half of device speed (can be used as input to SDRAM)
CLKMODE1
CLKMODE0
C6
C5
I
Clock mode select
Selects whether the output clock frequency = input clock frequency multiplied by 4, by 2, or by 1
PLLFREQ3
PLLFREQ2
PLLFREQ1
A9
D11
B10
I
PLL frequency range
Selects one of five frequency ranges bounding the CLKOUT1 signal
CLKOUT1 frequency determines the 3-bit value for the PLLFREQ pins
Reserved (pull-high with a dedicated 20-k
resistor)
PLL analog VCC connection for the low-pass filter (do not connect to board VCC)
PLL analog GND connection for the low-pass filter (do not connect to board GND)
RSV2
C11
I
PLLV
D12
A
A
A
PLLG
C12
PLLF
A11
PLL low-pass filter connection to external filter components and a bypass capacitor
EMULATION
TMS
L3
I
IEEE Std. 1149.1 Test access port (TAP) mode select
TDO
W2
O/Z
IEEE Std. 1149.1 TAP data out
TDI
R4
I
IEEE Std. 1149.1 TAP data in
TCLK
R3
I
IEEE Std. 1149.1 TAP clock
TRST
T1
I
IEEE Std. 1149.1 TAP reset
EMU1
Y1
I/O/Z
Emulation pin 1 (supports TI emulation hardware, but not part of IEEE Std. 1149.1 TAP)
EMU0
W3
I/O/Z
Emulation pin 0 (supports TI emulation hardware, but not part of IEEE Std. 1149.1 TAP)
CONTROL
RSV0
T2
I
Reserved for testing, pull high with a dedicated 20-k
resistor
Reserved for testing, should be pulled low with a dedicated 20-k
resistor
Device-compatibility mode first silicon. Pull up with a 20-k
resistor
Device reset
RSV1
G2
I
CMPTB
B9
I
RESET
K2
I
NMI
L2
I
Non-maskable interrupt
INT7
INT6
INT5
INT4
U3
V2
W1
U4
I
External interrupts
Edge-driven (rising edge)
IACK
Y2
O
Interrupt acknowledge for all active interrupts (not just external)
INUM3
INUM2
INUM1
INUM0
AA1
W4
AA2
AB1
O/Z
Active external-interrupt number
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt service fetch packet (ISFP) ordering
LENDIAN
H3
I
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
I = input, O = output, Z = high impedance
Analog signal (PLL filter)
P
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