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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 27/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
processor reset
Device reset begins immediately following the falling signal edge at the RESET pin. During reset, all functional
blocks of the processor are initialized to a known state as are all CPU and internal peripheral bus registers. The
EMIF-output signals (except HOLDA) and all HPI-output signals are put in the high-impedance state
immediately following the falling edge of RESET. They remain in the high-impedance state until the RESET
signal returns to a high level (see Figure 40). One of the signals, HACK, is driven low for the duration of the reset
signal.
Most of the HPI address pins have a special function during device reset. They become EMIF configuration pins
as shown on Figure 12. The lowest bit HPI-address pin becomes a memory-map-select pin (it also selects the
boot DMA transfer source address in future revisions). The selection of low or high state for that pin typically
depends on the processor start-up mode after reset (pins DC 13 to 11).
BOOT_SRC(2)
BOOT_SRC(1)
BOOT_SRC(0)
BOOT_CNT(2)
BOOT_CNT(1)
BOOT_CNT(0)
CE1_WIDTH(1)
CE1_WIDTH(0)
CE2_TYPE(1)
CE2_TYPE0)
CE0_TYPE(1)
CE0_TYPE(0)
MEM_BOOT
v
HA/DC16
HA/DC15
HA/DC14
HA/DC13
HA/DC12
HA/DC11
HA/DC10
HA/DC9
HA/DC8
HA/DC7
HA/DC6
HA/DC5
HA/DC4
HA/DC3
HA/DC2
HA/DC1
Not used during RESET
Startup mode after RESET
Boot DMA Transfer Count
(Words)
CE1 Space Memory Width
CE2 Space Memory Type
CE0 Space Memory Type
Memory-Map Select and
Source Address for the DMA
Boot Transfer
v
H
D
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
D
D
2
5
1
2
4
8
1
3
B
H
W
R
A
S
R
S
A
S
R
S
M
M
D
S
R
Figure 12. Device-Configuration Pins During Reset
P
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