- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383838 > ST20GP1 MAX 7000 CPLD 256 MC 208-PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁(yè)數(shù)： | 76/116頁(yè) |
| 文件大小： | 1107K |
| 代理商： | ST20GP1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)當(dāng)前第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
ST20-GP1
76/116
For 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples during
the stop bits is used to determine the effective stop bit value.
When the last stop bit has been received (at the end of the last programmed stop bit period) the
content of the receive shift register is transferred to the receive data buffer register
(
ASCRxBuffer
). The receive buffer full flag (
RxBufFull
) is set, and the parity (
ParityError
) and
framing error (
FrameError
) flags are updated, after the last stop bit has been received (at the end
of the last stop bit programmed period), regardless of whether valid stop bits have been received or
not. The receive circuit then waits for the next start bit (falling edge transition) at the
RXD
pin.
Reception is stopped by clearing the
RxEnable
bit. A currently received frame is completed
including the generation of the receive status flags. Start bits that follow this frame will not be
recognized.
Note
: In wake-up mode, received frames are only transferred to the receive buffer register if the ninth
bit (the wake-up bit) is 1. If this bit is 0, the receive buffer full (
RxBufFull
) flag will not be set and no
data will be transferred.
13.2 Hardware error detection capabilities
To improve the safety of serial data exchange, the ASC provides three error status flags in the
ASCStatus
register which indicate if an error has been detected during reception of the last data
frame and associated stop bits.
The parity error (
ParityError
) bit is set when the parity check on the received data is incorrect.
The framing error (
FrameError
) bit is set when the
RXD
pin is not a 1 during the programmed
number of stop bit times, sampled as described in the section above.
The overrun error (
OverrunError
) bit is set when the last character received in the
ASCRxBuffer
register has not been read out before reception of a new frame is complete.
These flags are updated simultaneously with the transfer of data to the receive buffer.
13.3 Baud rate generation
The ASC has its own dedicated 16-bit baud rate generator with 16-bit reload capability.
The baud rate generator is clocked with the CPU clock. The timer counts downwards and can be
started or stopped by the
Run
bit in the
ASCControl
register. Each underflow of the timer provides
one clock pulse. The timer is reloaded with the value stored in its 16-bit reload register each time it
underflows. The
ASCBaudRate
register is the dual-function baud rate generator/reload register. A
read from this register returns the content of the timer, writing to it updates the reload register.
An auto-reload of the timer with the content of the reload register is performed each time the
ASCBaudRate
register is written to. However, if the
Run
bit is 0 at the time the write operation to
the
ASCBaudRate
register is performed, the timer will not be reloaded until the first CPU clock
cycle after the
Run
bit is 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。