參數(shù)資料
型號: ST20GP1
英文描述: MAX 7000 CPLD 256 MC 208-PQFP
中文描述: GPS處理器
文件頁數(shù): 64/116頁
文件大?。?/td> 1107K
代理商: ST20GP1
ST20-GP1
64/116
LPAlarmLS and LPAlarmMS
The
LPAlarmLS
and
LPAlarmMS
registers are the least significant word and most significant word
of the
LPAlarm
register. This is used to program the low power alarm.
Table 10.5
LPAlarmLS
register format
Table 10.6
LPAlarmMS
register format
LPAlarmStart
A write to the
LPAlarmStart
register starts the low power alarm counter. The counter is stopped
and the
LPStart
register reset if either counter word (
LPTimerLS
and
LPTimerMS
) is written.
Table 10.7
LPAlarmStart
register format
LPSysPll
The
LPSysPll
register controls the System Clock PLL operation when low power mode is entered.
This allows a compromise between wake-up time and power consumption during stand-by.
Table 10.8
LPSysPll
register format
LPAlarmLS
LPC base address + #410
Read/Write
Bit
Bit field
Function
31:0
LPAlarmLS
Least significant word of the low power alarm.
LPAlarmMS
LPC base address + #414
Read/Write
Bit
Bit field
Function
7:0
LPAlarmMS
Most significant word of the low power alarm.
LPAlarmStart
LPC base address + #418
Write
Bit
Bit field
Function
0
LPAlarmStart
A write to this bit starts the low power alarm counter.
LPSysPll
LPC base address + #420
Read/Write
Bit
Bit field
Function
1:0
LPSysPll
Determines the system clock PLL when low power mode is entered, as follows:
LPSysPll1:0
System clock
00
PLL off
01
PLL reference on and power on
10
PLL reference on and power on
11
PLL on
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