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參數(shù)資料
| 型號： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁數(shù)： | 70/116頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
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12 Serial link interface (OS-Link)
The OS-Link based serial communications subsystem provides serial data transfer. Its main
function is for booting the device during software development.
The OS-Link is a serial communications engine consisting of two signal wires, one in each
direction. OS-Links use an asynchronous bit-serial (byte-stream) protocol, each bit received is
sampled five times, hence the term over-sampled links(OS-Links). The OS-Link provides a pair of
channels, one input and one output channel.
The OS-Link is used for the following purposes:
Bootstrapping — the program which is executed at power up or after reset can reside in
ROM in the address space, or can be loaded via the OS-Link directly into memory.
Diagnostics — diagnostic and debug software can be downloaded over the link connected
to a PC or other diagnostic equipment, and the system performance and functionality can
be monitored.
Communicating with OS-Link peripherals or other ST20 devices.
12.1 OS-Link protocol
The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed
by a one bit followed by eight data bits followed by a low stop bit (see Figure 12.1). The least
significant bit of data is transmitted first. After transmitting a data byte the sender waits for the
acknowledge, which consists of a high start bit followed by a zero bit. The acknowledge signifies
both that a process was able to receive the acknowledged data byte and that the receiving link is
able to receive another byte. The sending link reschedules the sending process only after the
acknowledge for the final byte of the message has been received. The link allows an acknowledge
to be sent before the data has been fully received.
Figure 12.1 OS-Link data and acknowledge formats
12.2 OS-Link speed
The OS-Link data rate is 19.6416 Mbits/s. This rate is the result of basing the clock on the
GPS-specific 16.368 MHz input. Standard 20 MHz development systems are
not
within
specification, but operate correctly under benign conditions. To operate within spec, the reference
clock for 5 MHz (B008, C011, C012) systems should be changed to 4.9104 MHz, for 10 MHz to
9.8208 MHz.
0
1
2
3
4
5
6
7
Data
Ack
H
H
L
L
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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