參數(shù)資料
型號： ST20GP1
英文描述： MAX 7000 CPLD 256 MC 208-PQFP
中文描述： GPS處理器
文件頁數(shù)： 67/116頁
文件大?。?/td> 1107K
代理商： ST20GP1
ST20-GP1
67/116
11 System services
The system services module includes the control system, the PLL and power control. System
services include all the necessary logic to initialize and sustain operation of the device and also
includes error handling and analysis facilities.
11.1 Reset, initialization and debug
The ST20-GP1 is controlled by a
notRST
pin which is a global power-on-reset. The CPU itself can
also be controlled by
CPUReset
and
CPUAnalyse
signals separately from the on-chip peripherals.
11.1.1 Reset
notRST
initializes the device and causes it to enter its boot sequence which can either be in off-
chip ROM or can be received down a link (see Section 11.2 on bootstrap).
notRST
must be
asserted at power-on.
When
notRST
is asserted low, all modules are forced into their power-on reset condition. The
clocks are stopped. The rising edge of
notRST
is internally synchronized and delayed until the
clocks are stable before starting the initialization sequence.
CPUReset
is provided as a functional reset which is quicker to reboot as the PLL is not reset. In
other respects the effect is the same as
notRST
.
CPUReset
can be used in conjunction with
CPUAnalyse
.
11.1.2 CPUAnalyse
If
CPUAnalyse
is taken high when the ST20-GP1 is running, the ST20-GP1 will halt at the next
descheduling point.
CPUReset
may then be asserted. When
CPUReset
comes low again the
ST20-GP1 will be in its reset state, and information on the state of the machine when it was halted
by the assertion of
CPUAnalyse
, is maintained permitting analysis of the halted machine.
An input link will continue with outstanding transfers. An output link will not make another access to
memory for data but will transmit only those bytes already in the link buffer. Providing there is no
delay in link acknowledgment, the link will be inactive within a few microseconds of the ST20-GP1
halting.
If
CPUAnalyse
is taken low without
CPUReset
going high the processor state and operation are
undefined.
11.1.3 Errors
Software errors, such as arithmetic overflow or array bounds violation, can cause an error flag to be
set. This flag is directly connected to the
ErrorOut
pin. The ST20-GP1 can be set to ignore the
error flag in order to optimize the performance of a proven program. If error checks are removed
any unexpected error then occurring will have an arbitrary undefined effect.The ST20-GP1 can
alternatively be set to halt-on-error to prevent further corruption and allow postmortem debugging.
The ST20-GP1 also supports user defined trap handlers, see Section 4.6 on page 23 for details.
If a high priority process pre-empts a low priority one, status of the
Error
and
HaltOnError
flags is
saved for the duration of the high priority process and restored at the conclusion of it. Status of both
flags is transmitted to the high priority process. Either flag can be altered in the process without
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