參數(shù)資料
型號: ST20GP1
英文描述: MAX 7000 CPLD 256 MC 208-PQFP
中文描述: GPS處理器
文件頁數(shù): 13/116頁
文件大?。?/td> 1107K
代理商: ST20GP1
ST20-GP1
13/116
is maintained between the satellite one-millisecond epochs and the receiver, despite time-of-
reception variations due to the varying path length from the satellite.
Figure 3.2 DSP packet format
3.1
DSP module registers
The GPS hardware channels of the ST20-GP1 are controlled by three sets of registers:
1
2
3
DSPControl
register
PRNcode0-11
and
PRNphase0-11
registers
NCOfrequency0-11
and
NCOphase0-11
registers
The base addresses for the DSP registers are given in the Memory Map chapter.
DSPControl register
The
DSPControl
register determines whether the PRN generators are on (normal use) or disabled
(for built-in-self-test of a system), whether the system is in tracking mode (840/970
μ
s output rate)
or initial acquisition mode (31/62
μ
s), and selects which of the two rates for each mode. It also
determines whether the accumulated carrier phase in the NCO are reset to zero automatically or
continue from their existing value. The bit allocations are given in Table 3.1.
62 byte packet every 840/970/31/62
μ
s
Absent 16-bit values padded with #8000
12 x 8-bit
time values
12 x 16-bit
Q values
12 x 16-bit
I values
16-bit
header
sync
sample
rate
Acquisition mode
First packet (in SV ms)
T[7:6] = 10
T[5:0] = time[5:0]
Remaining packets
T[7:6] = 00
T[5:0] = sequence number
(sequence numbers are 2 to
16 or 32)
Tracking mode
T[7:6] = 10
T[5:0] = time[5:0]
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