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參數(shù)資料
| 型號(hào)： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁數(shù)： | 63/116頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
63/116
Watchdog timer
The low power alarm counter is set to operate as a watchdog timer by setting the
WdEnable
register to 1. This disables entering low power mode when starting the timer. The low power alarm
is programmed and started as normal.
The
WdFlag
register can be read to determine if the device was reset by the
notRST
input or by a
watchdog time-out.
When the low power alarm counts down to the value #1, the
notWdReset
pin is asserted low for 1
low power clock cycle. In addition an internal reset of the ST20-GP1 is performed.
10.3 Low power configuration registers
The low power controller is allocated a 4k block of memory in the internal peripheral address
space. Information on low power mode is stored in registers as detailed in the following section.
The registers can be examined and set by the devlw (device load word) and devsw (device store
word) instructions, see Table 6.19 on page 43. Note, they can not be accessed using memory
instructions.
LPTimerLS and LPTimerMS
The
LPTimerLS
and
LPTimerMS
registers are the least significant word and most significant word
of the
LPTimer
register. This enables the least significant or most significant word to be written
independently without affecting the other word.
Table 10.2
LPTimerLS
register format
Table 10.3
LPTimerMS
register format
When the
LPTimer
register is written, the low power timer is stopped and the new value is
available to be written to the low power timer.
LPTimerStart
A write to the
LPTimerStart
register starts the low power timer counter. The counter is stopped
and the
LPTimerStart
register reset if either counter word (
LPTimerLS
and
LPTimerMS
) is
written.
Note, setting the
LPTimerStart
register to zero does not stop the timer.
Table 10.4
LPTimerStart
register format
LPTimerLS
LPC base address + #400
Read/Write
Bit
Bit field
Function
31:0
LPTimerLS
Least significant word of the low power timer.
LPTimerMS
LPC base address + #404
Read/Write
Bit
Bit field
Function
31:0
LPTimerMS
Most significant word of the low power timer.
LPTimerStart
LPC base address + #408
Write
Bit
Bit field
Function
0
LPTimerStart
A write to this bit starts the low power timer counter.
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PDF描述 |
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| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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