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參數(shù)資料
| 型號： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁數(shù)： | 74/116頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
74/116
Figure 13.2 8-bit data frames
9-bit data frames
9-bit data frames consist of:
nine data bits
D0-8
;
eight data bits
D0-7
plus an automatically generated parity bit;
eight data bits
D0-7
plus a wake-up bit.
Parity may be odd or even, depending on the
ParityOdd
bit in the
ASCControl
register. An even
parity bit will be set, if the modulo-2-sum of the eight data bits is 1. An odd parity bit will be cleared
in this case. The parity error flag (
ParityError
) will be set if a wrong parity bit is received. The parity
bit itself will be stored in bit 8 of the
ASCRxBuffer
register, see Table 13.4.
In wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit
(the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will
be transferred. This feature can be used to control communication in multi-processor systems.
When the master processor wants to transmit a block of data to one of several slaves, it first sends
out an address byte which identifies the target slave. An address byte differs from a data byte in
that the additional ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be
interrupted by a data byte. An address byte will interrupt all slaves (operating in 8-bit data + wake-
up bit mode), so each slave can examine the 8 least significant bits (LSBs) of the received
character (the address). The addressed slave will switch to 9-bit data mode, which enables it to
receive the data bytes that will be coming (with the wake-up bit cleared). The slaves that are not
being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes.
2nd
stop
bit
1st
stop
bit
start
bit
D0
(LSB)
8th
bit
Data bit (
D7
)
Parity bit
相關PDF資料 |
PDF描述 |
|---|---|
| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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