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參數(shù)資料
| 型號(hào)： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁數(shù)： | 10/116頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
10/116
Serial communications
The ST20-GP1 has two UARTs (Asynchronous Serial Controllers (ASCs)) for serial
communication. The UARTs provide an asynchronous serial interface and can be programmed to
support a range of baud rates and data formats, for example, data size, stop bits and parity.
There is one OS-Link on the ST20-GP1 which acts as a DMA engine independent of the CPU. The
OS-Link uses an asynchronous bit-serial (byte-stream) protocol, each bit received is sampled five
times, hence the term oversampled link(OS-Link). The OS-Link provides a pair of channels, one
input and one output channel. The link is used for:
bootstrapping during development,
debugging,
communicating with OS-Link peripherals or other ST20 devices.
Interrupt subsystem
The ST20-GP1 interrupt subsystem supports five prioritized interrupts. Three interrupts are
connected to on-chip peripherals (2 for the UARTs, 1 for the programmable IO) and two are
available as external interrupt pins.
All interrupts are at a higher priority than the high priority process queue. Each interrupt level has a
higher priority than the previous and each level supports only one software handler process.
Note that interrupt handlers must not prevent the GPS DSP data traffic from being handled. During
continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has
a 32
μ
s rate and thus all interrupts must be disabled except if used to stop GPS operation.
Byte-wide parallel port
The byte-wide parallel port is provided to communicate with an external device. It transfers a byte
at a time, operating half duplex in the program-selected direction.
Parallel IO module
Six bits of parallel IO are provided. Each bit is programmable as an output or an input. Edge
detection logic is provided which can generate an interrupt on any change of an input bit.
System services module
The ST20-GP1 system services module includes:
reset, initialization and error port.
phase locked loop (PLL) — accepts 16.368 MHz input and generates all the internal high
frequency clocks needed for the CPU and the OS-Link.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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