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| 型號(hào)： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁(yè)數(shù)： | 65/116頁(yè) |
| 文件大小： | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
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SysRatio
The
SysRatio
register is a read only register and gives the speed at which the system PLL is running.
It contains the relevant PLL multiply ratio when using the PLL, or contains the value ‘1’ when in
TimesOneMode
for the PLL.
Table 10.9
SysRatio
register format
WdEnable
Setting the
WdEnable
register enables the low power alarm counter to be used as a watchdog
timer.
Table 10.10
WdEnable
register format
WdFlag
This register can be used to determine if the device was reset by the
notRST
input or by a
watchdog time-out.
Note that this bit is not reset by the
CPUReset
input.
Table 10.11
WdFlag
register format
10.4 Clocking sources
The low power timer and alarm must be clocked at all times by one of the following clocking sources:
External clock input (
LPClockIn
) — this clock must not be more than one eighth of the sys-
tem clock rate. In this case the
LPClockOsc
pin should not be connected on the board.
Watch crystal, as in Figure 10.1.
SysRatio
LPC base address + #500
Read
Bit
Bit field
Function
5:0
SysRatio
PLL speed, as follows:
SysRatio PLL
1
2
4
6
x1
x1
x2
x3
TimesOneMode
16.368 MHz
32.736 MHz
RESERVED
WdEnable
LPC base address + #510
Read/Write
Bit
Bit field
Function
0
WdEnable
Determines whether the low power alarm is set to operate as an alarm or as a
watchdog timer.
0
alarm
1
watchdog
WdFlag
LPC base address + #514
Read
Bit
Bit field
Function
0
WdFlag
Watchdog timer flag.
0
set to 0 by an external
notRST
1
set to 1 when the watchdog counter is #1 and the
WdEnable
register is 1
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相關(guān)代理商/技術(shù)參數(shù) |
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| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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