參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 59/92頁
文件大小： 1823K
代理商： ORT82G5
Agere Systems Inc.
59
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Pin Information
(continued)
Table 23. FPGA Common-Function Pin Description
(continued)
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Symbol
I/O
Description
PPC_A[14:31]
A[17:0]
MPI_BURST
MPI_BDIP
MPI_TSZ[1:0]
A[21:0]
I
During MPI mode, the PPC_A[14:31] are used as the address bus driven by the
PowerPC
bus master utilizing the least significant bits of the
PowerPC
32-bit address.
During master parallel configuration mode, A[14:31] address the configuration EPROM. In
MPI mode, many of the A[n] pins have alternate uses as described below. See the special
function blocks section for more MPI information. During configuration, if not in master par-
allel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled.
MPI_BURST is driven low to indicate a burst transfer is in progress. Driven high indicates
that the current transfer is not a burst.
MPI_BDIP is driven by the
PowerPC
processor assertion of this pin indicates that the sec-
ond beat in front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size for
the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
During master parallel mode A[14:31], MPI_BURST, MPI_BDIP and MPI_TSZ address the
configuration EPROMs up to 4 Mbytes.
If not used for MPI, these pins are user-programmable I/O pins.*
In
PowerPC
mode MPI operation, this is driven low indicating the MPI received the data on
the write cycle or returned data on a read cycle.
This is the
PowerPC
synchronous, positive-edge bus clock used for the MPI interface. It can
be a source of the clock for the embedded system bus. If MPI is used, this can be the
AMBA
bus clock.
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
the internal system bus for the current transaction.
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O Selectable data bus width from 8-, 16-, 32-bit. Driven by the bus master in a write transac-
tion. Driven by MPI in a read transaction.
I
D[7:0] receive configuration data during master parallel, peripheral, and slave parallel con-
figuration modes and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input.
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
After configuration, the pins are user-programmable I/O pins.*
I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for
D[16:23], and DP[3] for D[24:32].
After configuration, this pin is a user-programmable I/O pin.*
I
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input.
During configuration, a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
O
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After configuration, DOUT is a user-programmable I/O pin.*
O
MPI_ACK
O
MPI_CLK
I
MPI_TEA
O
MPI_RTRY
D[0:31]
O
DP[0:3]
DIN
DOUT
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