參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 15/92頁(yè)
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
15
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
ORT82G5 Overview
(continued)
FPGA Interface
The FPGA logic will receive/transmit frame-aligned
(optional for 8b/10b mode) 32-bit streams of up to
77.8 MHz data (maximum of eight streams in each
direction) from/to the embedded core. All frames trans-
mitted to the FPGA can be aligned using comma char-
acters or code violation from each channel, and a
single aligned frame pulse is provided to the FPGA
logic for each group of aligned channels. For transmit,
the generation of a comma or code violation that can
be found by the receiving device on the other side of
the serial link is created through an independent con-
trol signal per channel.
If the receive channel alignment FIFOs are bypassed,
then each channel will provide its own receive clock
and K character detect signals. If the 8b/10b decoders
are bypassed, then 40-bit data streams are passed to
the FPGA logic. No frame pulses are available in this
case and channel alignment cannot be performed.
FPSC Configuration
Configuration of the ORT82G5 occurs in two stages:
FPGA bitstream configuration and embedded core
setup.
FPGA Configuration
Prior to becoming operational, the FPGA goes through
a sequence of states, including powerup, initialization,
configuration, start-up, and operation. The FPGA logic
is configured by standard FPGA bit stream configura-
tion means as discussed in the Series 4 FPGA data
sheet. The options for the embedded core are set via
registers that are accessed through the FPGA system
bus. The system bus can be driven by an external
Pow-
erPC
compliant microprocessor via the MPI block or via
a user master interface in FPGA logic. A simple IP
block, that drives the system by using the user register
interface and very little FPGA logic, is available in the
MPI/System Bus Application Note
. This IP block sets
up the embedded core via a state machine and allows
the ORT82G5 to work in an independent system with-
out an external microprocessor interface.
Backplane Transceiver Core Detailed
Description
SERDES
A detailed block diagram of the receive and transmit
data paths for a single channel of the SERDES is
shown in Figure 3.
The transmitter section accepts either 8-bit unencoded
data or 10-bit encoded data at the parallel input port. It
also accepts the low-speed reference clock at the REF-
CLK input and uses this clock to synthesize the internal
high-speed serial bit clock. The serialized data are
available at the differential CML output terminated in
50
or 75
to drive either an optical transmitter or
coaxial media or circuit board/backplane.
The receiver section receives high-speed serial data at
its differential CML input port. These data are fed to the
clock recovery section which generates a recovered
clock and retimes the data. This means that the receive
clocks are asynchronous between channels. The
retimed data are deserialized and presented as a 10-bit
encoded or a 8-bit unencoded parallel data on the out-
put port. Two-phase receive byte clocks are available
synchronous with the parallel words. The receiver also
optionally recognizes the comma characters or code
violations and aligns the bit stream to the proper word
boundary.
Bias Section
A fractional band-gap voltage generator is included on
the design. An external resistor (3.32 k
± 1%), con-
nected between the pins REXT and VSSREXT gener-
ates the bias currents within the chip. This resistor
should be able to handle at least 300 μA.
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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