參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 20/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
20
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Data from a SERDES channel appears in 10-bit raw form or 8-bit decoded form at the SRBDx[9:0] port (where x is
a placeholder for one of the letters, A-D) with a latency of approximately 14 cycles. Accompanying this data are the
comma-character indicator (SBYTSYNCx), clocks (SRBC0x, and SRBC1x), link-state indicator (SWDSYNCx), and
code-violation indicator (SCVx).
With the 8B10BR control bit of the SERDES channel set to 1, the data presented at SRBDx[9:0] will be decoded
characters. Bit 8 will indicate whether SRBDx[7:0] represents an ordinary data character (bit 8 == 0), or whether
SRBDx[7:0] represents a special character, like a comma. When 8B10BR is set to 0, the data at SRBDx[9:0] will be
encoded characters. The XAUI link-state machine should not be used in this mode of operation. When in XAUI
mode, the MUX/deMUX looks for /A/ (as defined in
IEEE
802.3ae v.2.1) characters for channel alignment and
requires the characters to be in decoded form for this to work.
2265(F)
Figure 5. ORT82G5 Receive Path for a Single SERDES Channel
8
E
100
—
156 MHz
REFERENCE
PLL & CDR
CLOCK
HDINPx,
HDINNx
RECEIVE DATA
1.0
—
3.125 Gbits/s
1:4
DE-
MULTIPLEXER
(X 10)
XAUI LINK
STATE
MACHINE
EMBEDDED CORE
1
M
C
A
L
M
SRBDx[9:0]
SBYTSYNCx
SRBC0x
SCVx
25
—
78 MHZ
CLOCK
COMMADET
4 K_CTRL
32 DATA
M
A
FIFO
2:1
MULTIPLEXER
(X 40)
DATA
40
DATA
36
SERDES
BLOCK
MUX/DEMUX
BLOCK
CHANNEL ALIGN
BLOCK
SWDSYNCx
SRBC1x
p
q
r
s
t
x
y
z
SRBDx[9:0]
SRBC0x
SRBC1x
SBYTSYNCx,
SVCx
SWDSYNCx
q0
r8r9s0
p4p5p6p7p8p9
p0p1p2p3
r2r3r4
r5
r6
r7
s1s2s3s4
p
HDINx
SRBDx[9:0]
1-bit
10-bit
LATENCY =
APPROX 23 CLOCKS
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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