參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 33/92頁
文件大小： 1823K
代理商： ORT82G5
Agere Systems Inc.
33
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Parallel Loopback at the SERDES Boundary
The parallel loopback involves the parallel buses LDIN[9:0] and LDOUT[9:0]. The loopback connection is made
such that LDIN[9:0] is logically equivalent to LDOUT[9:0]. In the parallel loopback mode, the LDOUT[9:0] pins
remain active. The receive data are sourced at the HDINP HDINN pins and detected at the HDOUTP HDOUTN
pins. The device is otherwise in its normal mode of operation. The data rate selection bits TXHR and RXHR in the
channel configuration registers must be configured to carry the same value and the PRBS generator and checker
are excluded by setting the PRBS configuration bit to 0. Also, the 8b/10b encoder and decoder are excluded from
the loopback path by setting the 8b10bT and 8b10bR configuration bits to 0. Table 10 illustrates the control inter-
face register configuration for the parallel loopback.
Table 10. Parallel Loopback Configuration
Parallel Loopback at MUX/DeMUX Boundary Excluding SERDES
This is a low-frequency testmode. This parallel loopback involves the parallel buses SRBDx[9:0] and STBDx[9:0].
The loopback connection is made such that SRBDx[9:0] is logically equivalent to STBDx[9:0] and STBDx[9:0]
remains active, thus bypassing the SERDES. Data can be sent from the FPGA through TWDxx signals and moni-
tored on MRWDxx signals. This test is enabled by setting the pin PLOOP_TEST_ENN to 1. PASB_TESTCLK must
be running in this mode at 4x frequency of RSYS_CLK[A, B] or TSYS_CLK[A, B].
Register
Address
Bit Value
Bit Name
Comments
30002, 30012, 30022, 30032,
30102, 30112, 30122, 30132
30002, 30012, 30022, 30032,
30102, 30112, 30122, 30132
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to
the same value.
Set to 0. The 8b/10b encoder is excluded from the
loopback path. The 8b/10b encoder and decoder
selection control bits must both be set to 0.
Set to 0 or 1. TXHR and RXHR bits must be set to
the same value.
Set to 0. The 8b/10b decoder is excluded from the
loopback path. The 8b/10b encoder and decoder
selection control bits must both be set to 0.
Set to 0.
Bit 7 = 0
8B10BT
30003, 30013, 30023, 30033,
30103, 30113, 30123, 30133
30003, 30013, 30023, 30033,
30103, 30113, 30123, 30133
Bit 0 = 0 or 1
RXHR
Bit 3 = 0
8B10BR
30004, 30014, 30024, 30034,
30104, 30114, 30124, 30134
30004, 30014, 30024, 30034,
30104, 30114, 30124, 30134
Bit 0 = 0
PRBS
Bit 7 = 1
—
Set to 1 if the loopback is done on a per-channel
basis.
However, if the loopback is done globally on all
the four
channels, this bit can be set to 0 but bit 7 of regis-
ter 5
must be set to 1.
Set to 1 if the loopback is done globally on all four
channels.
Set to 00001.
30005, 30105
Bit 7 = 1
—
30006, 30106
Bits[4:0] =00001
—
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