參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 16/92頁(yè)
文件大?。?/td> 1823K
代理商： ORT82G5
16
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Reset Operation
The SERDES block can be reset in one of three different ways as follows: on power up, using the hardware reset,
or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to
approximately 80% of the nominal value of 1.5 V. Following this event, the device will be ready for normal operation
after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES channels and resets all microprocessor and internal registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the
channel configuration register. The device will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four
channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be ready for nor-
mal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES
internal registers and counters. The microprocessor registers are not affected. It should also be noted that the
embedded block cannot be accessed until after FPGA configuration is complete.
Start Up Sequence
1.
Initiate a hardware reset by making PASB_RESETN low for 100 ns. The device will be ready for operation 3 ms
after the low to high transition of PASB_RESETN. During this time configure the FPGA portion of the device.
Wait for 100 ns. Configure the following SERDES internal and external registers.
Set the following bits in register 30800:
—
Bits LCKREFN_[AD:AA] to 1, which implies lock to data.
—
Bits ENBYSYNC_[AD:AA] to 1 which enables dynamic alignment to comma.
2.
Set the following bits in register 30801:
—
Bits LOOPENB_[AD:AA] to 1 if loopback is desired.
Set the following bits in register 30900:
—
Bits LCKREFN_[BD:BA] to 1 which implies lock to data.
—
Bits ENBYSYNC_[BD:BA] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30901:
—
Bits LOOPENB_[BD:BA] to 1 if loopback is desired.
Set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132:
—
TXHR[0:3] set to 1 if TX half-rate is desired.
—
8B10BT[0:1] set to 1
Set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133:
—
RXHR[0:3] Set to 1 if RX half-rate is desired.
—
8B10BR[0:3] set to 1.
Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30110, 30120, 30130:
—
LKI-PLL lock indicator. 1 indicates that PLL has achieved lock.
—
SDON-Signal detect output indicator. 0 indicates active data.
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