參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 5/92頁(yè)
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
5
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Programmable Features
I
High-performance programmable logic:
—
0.13 μm 7-level metal technology.
—
Internal performance of >250 MHz.
—
Over 400k usable system gates.
—
Meets multiple I/O interface standards.
—
1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
I
Traditional I/O selections:
—
LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
—
Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
—
Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
—
Two slew rates supported (fast and slew-limited).
—
Fast-capture input latch and input flip-flop
(FF)/latch for reduced input setup time and zero
hold time.
—
Fast open-drain drive capability.
—
Capability to register 3-state enable signal.
—
Off-chip clock drive capability.
—
Two-input function generator in output path.
I
New programmable high-speed I/O:
—
Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, IV), ZBT, and
DDR.
—
Double-ended: LVDS, bused-LVDS, and LVPECL.
Programmable, parallel termination (100
) is
also supported for these I/Os.
—
Customer defined: ability to substitute arbitrary
standard cell I/O to meet fast-moving standards.
I
New
capability to (de)multiplex I/O signals:
—
New DDR on both input and output at rates up to
311 MHz (622 MHz effective rate).
—
New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
I
Enhanced twin-quad programmable function unit
(PFU):
—
Eight 16-bit look-up tables (LUTs) per PFU.
—
Nine user registers per PFU, one following each
LUT, and organized to allow two nibbles to act
independently, plus one extra for arithmetic opera-
tions.
—
New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
—
New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4
→
1 MUX, new
8
→
1 MUX, and ripple mode arithmetic functions
in the same PFU.
—
32 x 4 RAM per PFU, configurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
—
Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing which reduces rout-
ing congestion and improves speed.
—
Flexible fast access to PFU inputs from routing.
—
Fast-carry logic and routing to all four adjacent
PFUs for nibble-wide, byte-wide, or longer arith-
metic functions, with the option to register the
PFU carry-out.
I
Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
I
Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
I
SLIC provides eight 3-statable buffers, up to a 10-bit
decoder, and
PAL
-like and-or-invert (AOI) in each
programmable logic cell.
I
New 200 MHz embedded quad-port RAM blocks,
2 read ports, 2 write ports, and 2 sets of byte lane
enables. Each embedded RAM block can be config-
ured as:
—
1
—
512 x 18 (quad-port, two read/two write) with
optional built in arbitration.
—
1
—
256 x 36 (dual-port, one read/one write).
—
1
—
1k x 9 (dual-port, one read/one write).
—
2
—
512 x 9 (dual-port, one read/one write for
each).
—
2 RAMS with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
—
Supports joining of RAM blocks.
—
Two 16 x 8-bit content addressable memory
(CAM) support.
—
FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
—
Constant multiply (8 x 16 or 16 x 8).
—
Dual variable multiply (8 x 8).
I
Embedded 32-bit internal system bus plus 4-bit par-
ity interconnects FPGA logic, microprocessor inter-
face (MPI), embedded RAM blocks, and embedded
standard cell blocks with 66 MHz bus performance.
Included are built-in system registers that act as the
control and status center for the device.
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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