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參數(shù)資料
| 型號(hào)： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金 |
| 文件頁(yè)數(shù)： | 22/92頁(yè) |
| 文件大?。?/td> | 1823K |
| 代理商： | ORT82G5 |
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22
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed
Description
(continued)
Byte Alignment
When ENBYSYNC = 1, the ORT82G5 recognizes the
comma sequence and aligns the 10-bit comma con-
taining character to the word boundary. BYTSYNC = 1
when the parallel output word contains a byte-aligned
comma containing character. The BYTSYNC flag will
continue to pulse a logic 1 whenever a byte aligned
comma containing character is at the parallel output
port.
Link State Machines
Two link state machines are included in the ORT82G5,
one for XAUI applications and a second for fibre-chan-
nel applications.
The fibre-channel link state machine is responsible for
establishing a valid link between the transmitter and the
receiver and for maintaining link synchronization. The
machine wakes up in the loss of synchronization state
upon powerup reset. This is indicated by
WDSYNC = 0. While in this state, the machine looks for
a particular number of consecutive idle ordered sets
without any invalid data transmission in between before
declaring synchronization achieved. Synchronization
achieved is indicated by asserting WDSYNC = 1. Spe-
cifically, the machine looks for three continuous idle
ordered sets without any misaligned comma character
or any running disparity based code violation in
between. In the event of any such code violation, the
machine would reset itself to the ground state and start
its search for the idle ordered sets again.
In the synchronization achieved state, the machine
constantly monitors the received data and looks for any
kind of code violation that might result due to running
disparity errors. If it were to receive four such consecu-
tive invalid words, the link machine loses its synchroni-
zation and once again enters the loss of
synchronization state (LOS). A pair of valid words
received by the machine overcomes the effect of a pre-
viously encountered code violation. LOS is indicated by
the status of WDSYNC output which now transitions
from 1 to 0. At this point the machine attempts to estab-
lish the link yet again. Figure 6 shows the state diagram
for the fibre-channel link state machine.
2266(F)
Figure 6. Fibre-Channel Link State Machine State Diagram
LOS = 1
OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER)
VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION)
CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION)
VW
RST
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1)
OS
CV
OS
OS
OS
CV
CV
CV
CV
CV
VW
VW
VW
2 VW
2 VW
2 VW
a
b
c
d
e
h
g
f
LOSS OF SYNCHRONIZATION (WDSYNC = 0)
LSM_ENABLE
+
POWERUP RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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