參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 2/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
Table of Contents
Contents
Page
Contents
Page
2
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Introduction..................................................................1
Embedded Function Features.....................................4
Intellectual Property Features......................................4
Programmable Features..............................................5
Programmable Logic System Features.......................6
Description...................................................................7
What Is an FPSC ....................................................7
FPSC Overview .........................................................7
FPSC Gate Counting ................................................7
FPGA/Embedded Core Interface ..............................7
ORCA
Foundry 2000 Development System .............7
FPSC Design Kit .......................................................8
FPGA Logic Overview ...............................................8
PLC Logic ..................................................................8
Programmable I/O .....................................................9
Routing ......................................................................9
System-Level Features..............................................10
Microprocessor Interface .........................................10
System Bus .............................................................10
Phase-Locked Loops ..............................................10
Embedded Block RAM ............................................10
Configuration ...........................................................11
Additional Information .............................................11
ORT82G5 Overview..................................................11
Device Layout .........................................................11
Backplane Transceiver Interface .............................11
ORT82G5 Overview (continued)...............................12
Serializer and Deserializer (SERDES) ....................14
MUX/DeMUX Block .................................................14
Multichannel Alignment FIFOs ................................14
XAUI or Fibre-Channel Link State Machine ............14
Dual Port RAMs ......................................................14
FPGA Interface .......................................................15
FPSC Configuration ................................................15
Backplane Transceiver Core Detailed Description....15
SERDES .................................................................15
SERDES Transmit Path (FPGA
Backplane) ......18
Transmit Preemphasis and Amplitude Control ........19
SERDES Receive Path (Backplane
FPGA) .......19
8b/10b Encoding/Decoding .....................................21
SERDES Transmit and Receive PLLs ................... 21
Reference Clock ..................................................... 21
Byte Alignment ....................................................... 22
Link State Machines ............................................... 22
XAUI Link Synchronization Function ...................... 23
MUX/DeMUX Block ................................................ 25
Multichannel Alignment (Backplane
FPGA) ....... 27
Alignment Sequence .............................................. 29
Loopback Modes .................................................... 32
High-Speed Serial Loopback .................................. 32
Parallel Loopback at the SERDES Boundary ......... 33
Parallel Loopback at MUX/DeMUX Boundary
Excluding SERDES ............................................... 33
ASB Memory Blocks ............................................... 34
Memory Map............................................................. 36
Definition of Register Types ................................... 36
Absolute Maximum Ratings...................................... 54
Recommended Operating Conditions ...................... 54
HSI Electrical and Timing Characteristics ................ 54
Pin Information ......................................................... 57
Power Supplies for ORT82G5 ................................ 63
Recommended Power Supply Connections ........... 64
Recommended Power Supply Filtering Scheme .... 64
Package Pinouts .................................................... 69
Pin Information ......................................................... 70
Package Thermal Characteristics
Summary.................................................................. 87
Θ
JA ......................................................................... 87
ψ
JC ........................................................................ 87
Θ
JC ........................................................................ 87
Θ
JB ........................................................................ 87
FPSC Maximum Junction Temperature ................. 87
Package Thermal Characteristics............................. 88
Package Coplanarity ................................................ 88
Package Parasitics................................................... 88
Package Outline Diagrams....................................... 89
Terms and Definitions ............................................ 89
680-Pin PBGAM ..................................................... 90
Hardware Ordering Information................................ 91
Software Ordering Information ................................. 91
相關(guān)PDF資料
PDF描述
ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
OS1001 Interface IC
OS1010 Optoelectronic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*