參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 25/92頁(yè)
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
25
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed
Description
(continued)
MUX/DeMUX Block
Transmit Path (FPGA
→
Backplane)
The MUX is responsible for taking 36 bits of data/con-
trol at the low-speed transmit interface and up-convert-
ing it to 9 bits of data/control at the SERDES transmit
interface.
The MUX has 2 clock domains: one based on a clock
received from the SERDES; the other that comes from
the FPGA at 1/4 the frequency of the SERDES clock.
The time sequence of interleaving data/control values
is shown in Figure 8 below.
The low-speed transmit interface consists of a clock,
4 data byte values and a control bit for each of the byte
values. The data bytes are conveyed to the MUX via
the TWDx[31:0] ports. The control bits are TCOM-
MAx[3:0]. The clock is TSYS_CLK(A, B).
Both the data and control are strobed into the MUX at
this interface on the rising edge of TSYS_CLK(A, B).
Besides taking in a clock for capture, the interface
sends back a clock of the same frequency, but arbitrary
phase. This clock, TCK78, is derived from one of the 4
channels of MUX. Within each MUX is a divide-by-4 of
the SERDES TBCx311 clock used in synchronizing the
transmit data words to the TBCx311 clock domain.
TCKSEL[1:0] bits select the source channel of TCK78.
When TCKSEL[1:0] is 00, the clock source is channel
A, 01 is channel B, 10 is channel C, and 11 is channel
D. In many cases, this TCK78 clock is used to drive the
low-speed clock in the FPGA that is connected to the
TSYS_CLK(A, B) signal.
2267(F)
Figure 8. Transmit MUX Block for a Single SERDES Channel
PLL
8B/10B
ENCODER
10
32
4
8
TSYS_CLK(A, B)
TCOMMAx[3:0]
EMBEDDED CORE
FPGA
DATA BYTE
STBDx[7:0]
K-CONTROL
STBDx[8]
GROUND
STBDx[9]
9
STBC311x
SERDES
BLOCK
MUX
BLOCK
p
q
r
s
t
x
y
z
STBDx[9:0]
TCOMMAx[3:0]
LATENCY = 4 TSYS_CLK (A, B) CLOCKS
TWDx[31:0]
PARALLEL
TO
SERIAL
(X 9)
DIVIDE
BY 4
FIFO
MUX
4 CHANNELS
TCKSEL[1:0]
TCK78(A,B)
TWDx[31:0]
TSYS_CLK (A, B)
p7-0
p8
40-bit
q7-0r7-0s7-0
t7-0x7-0y7-0z7-0
s8
q8
r8
t8
z8
x8
y8
10-bit (THE MSB ALWAYS TIED TO LOGIC 0)
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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