參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 39/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
39
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Transmit Channel Configuration Registers (Continued)
30032
TXHR_AD
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel
D. When
TXHR = 1,
the transmit-
ter samples
data on the
falling edge
of the TBC
clock. When
TXHR = 0,
the transmit-
ter samples
data on the
falling edge
of the double
rate clock
(derived from
TBC). TXHR
= 0 on device
reset.
PWRDNT_A
D
Transmit
Powerdown
Control Bit,
Bank A,
Channel D.
When
PWRDNT =
1, sections of
the transmit
hardware are
powered
down to con-
serve power.
PWRDNT = 0
on device
reset.
PE0_AD
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel D.
PE0,
together with
PE1, selects
one of three
preemphasis
settings for
the transmit
section. PE0
= 0 on device
reset.
PE1_AD
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel D.
PE1,
together with
PE0, selects
one of three
preemphasis
settings for
the transmit
section. PE1
= 0 on device
reset.
HAMP_AD
Transmit Half
Amplitude
Selection Bit,
Bank A,
Channel D.
When HAMP
= 1, the
transmit out-
put buffer
voltage swing
is limited to
half its ampli-
tude. Other-
wise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_A
D
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel
D. When
TBCKSEL =
0, the internal
XCK is
selected.
Otherwise,
the TBC
clock is
selected.
TBCKSEL =
0 on device
reset.
RINGOVR_A
D
Transmit Ring
Counter Bub-
ble Detector
Alarm Over-
ride Control
Bit, Bank A,
Channel D.
When RIN-
GOVR = 0,
the bubble
detector
alarm is
effective.
Otherwise,
the bubble
detector
alarm is not
effective.
RINGOVR =
0 on device
reset.
8B10BT_AD
Transmit 8B/
10B Encoder
Enable Bit,
Bank A,
Channel D.
When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
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ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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