參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 48/92頁(yè)
文件大小： 1823K
代理商： ORT82G5
48
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES B Receive Channel Configuration Registers
30103
RXHR_BA
Receive Half Rate
Selection Bit, Bank B,
Channel A. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BA
Receiver Power
Down Control Bit,
Bank B, Channel A.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_BA
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel A. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
SDOVRIDE_BB
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel B. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
SDOVRIDE_BC
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel C. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
SDOVRIDE_BD
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel D. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_BA
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel A.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise, it
is bypassed. 8B10BR
= on device reset.
LINKSM_BA
Link State Machine
Enalbe Bit, Bank B,
Channel A. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
30113
RXHR_BB
Receive Half Rate
Selection Bit, Bank B,
Channel B. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BB
Receiver Power
Down Control Bit,
Bank B, Channel B.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
8B10BR_BB
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel B.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise, it
is bypassed. 8B10BR
= on device reset.
LINKSM_BB
Link State Machine
Enalbe Bit, Bank B,
Channel B. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
30123
RXHR_BC
Receive Half Rate
Selection Bit, Bank B,
Channel C. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BC
Receiver Power
Down Control Bit,
Bank B, Channel C.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
8B10BR_BC
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel C.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise, it
is bypassed. 8B10BR
= on device reset.
LINKSM_BC
Link State Machine
Enalbe Bit, Bank B,
Channel C. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
30133
RXHR_BD
Receive Half Rate
Selection Bit, Bank B,
Channel D. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BD
Receiver Power
Down Control Bit,
Bank B, Channel D.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
8B10BR_BD
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel D.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise, it
is bypassed. 8B10BR
= on device reset.
LINKSM_BD
Link State Machine
Enalbe Bit, Bank B,
Channel D. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
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