參數(shù)資料
型號(hào)： OR3TP12-6BA352
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 94/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
94
L Lucent Technologies Inc.
Timing Characteristics
(continued)
PFU Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
Combinational PFU Timing Characteristics
I
Sequential PFU Timing Characteristics
I
Ripple Mode PFU Timing Characteristics
I
Synchronous Memory Write Characteristics
I
Synchronous Memory Read Characteristics
PLC Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
PFU Output MUX and Direct Routing Timing Charac-
teristics
SLIC Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
Supplemental Logic and Interconnect Cell (SLIC)
Timing Characteristics
PIO Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
Programmable I/O (PIO) Timing Characteristics
Special Function Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
Microprocessor Interface (MPI) Timing Characteris-
tics
I
Programmable Clock Manager (PCM) Timing Char-
acteristics
I
Boundary-Scan Timing Characteristics
Clock Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
ExpressCLK
(ECLK) and Fast Clock (FCLK) Timing
Characteristics
I
General-Purpose Clock Timing Characteristics
(Internally Generated Clock)
I
OR3TP12
ExpressCLK
to Output Delay (Pin-to-Pin)
I
OR3TP12 Fast Clock (FCLK) to Output Delay (Pin-
to-Pin)
I
OR3TP12 General System Clock (SCLK) to Output
Delay (Pin-to-Pin)
I
OR3TP12 Input to ExpressCLK (ECLK) Fast Capture
Set-Up/Hold Time (Pin-to-Pin)
I
OR3TP12 Input to Fast Clock Setup/Hold Time (Pin-
to-Pin)
I
OR3TP12 Input to General System Clock Setup/Hold
Time (Pin-to-Pin)
Configuration Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
General Configuration Mode Timing Characteristics
I
Master Serial Configuration Mode Timing Character-
istics
I
Asynchronous Peripheral Configuration Mode Timing
Characteristics
I
Slave Serial Configuration Mode Timing Characteris-
tics
I
Microprocessor Interface Timing Characteristics
Readback Timing
Refer to ORCA OR3C/Txxx Series data sheet for the
following:
I
Readback Timing Characteristics
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
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