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參數(shù)資料
| 型號： | OR3TP12-6BA352 |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 53/128頁 |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA352 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
53
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed
Description
Target FIFO Interface
Overview
The Target FIFO interface consists of two transfer
phases: command/address followed by data. This
sequence must be followed with the assertion of
twlastcycn
indicating the completion of each phase.
The PCI address and command are always provided by
the Target FIFO interface with the address transferred
on the data paths for the specific mode. In any port
mode, the command and address are transferred dur-
ing the same cycle with the Target command trans-
ferred on a separate bus
tcmd
. The command/address
phase is followed by data transfer. For Target writes,
write data with byte enables will be provided from the
Target, whereas for Target reads, the Target will receive
its data from the FPGA application. All types of data
are transferred on the data paths defined by the opera-
tional mode (dual- or quad-port).
Target State Counter
The Target FIFO interface provides a state counter,
tstatecntr[3:0]
, that informs the FPGA application of
its current state (Table 19). This state counter deter-
mines what data is being provided to the FPGA appli-
cation by the Target FIFO interface during the
command/address or write data phases, or what is
expected from the FPGA application during the read
data phases. The state counter transitions from one
state to another in a predetermined manner. Table 20
through Table 23 detail the sequencing of the
tstate-
cntr
and the data transferred for Target write and read
transactions.
The value on bus
tstatecntr
can be used to minimize
FPGA logic or verify proper operation. The data pro-
vided by the Target FIFO interface to the FPGA appli-
cation is accompanied by a value on
tstatecntr[3:0]
.
This value can be directly used by the FPGA applica-
tion to determine the proper orientation of the Target
command, address and/or write data. This eliminates
the need for logic in the FPGA to duplicate a state
counter. The data required from the FPGA application
by the Target during the read data phase is also
defined by the value on
tstatecntr
. However, the state
counter value being sent to the FPGA is in the same
cycle that the data is sent from the FPGA application.
Here, the value provided by the Target FIFO interface
can be used to determine the next state, since current
since current data, phase, enables, and state transi-
tions are known.
Target Address Compare and BAR Size
The Target FIFO interface provides the following two
features to reduce overhead when transferring the PCI
start Target address during the command/address
phase. First, the Target FIFO interface detects the page
size of the base address register (BAR) that decoded
the current PCI address, and only transfers the address
bytes necessary to cover the page size.
Second, the Target FIFO interface provides a holding
register which is used to compare the address of the
previous Target transaction to the current one. If there
is a match, the most signification address information is
not transferred, providing the BAR size is greater than
the data bus size for quad- or dual-port mode. This will
cover address bits [63:48] in quad-port and bits [63:32]
in the dual-port mode. This option is enabled through
the FPSC configuration manager of the FPSC design
kit.
Target Write Operation
Delayed Transactions, Target Memory Write
Target memory write operations cannot be processed
as delayed (delayed transactions: PCI Specification
2.2: Section 3.3.3.3), and are always posted. The Tar-
get will only retry a memory write transaction if a cur-
rent Target transaction is in progress (
treqn
is
asserted) or
t_retryn
is asserted. Once the Target
determines that it is the intended recipient, it asserts
devseln
and
trdyn
and begins storing data into the
Target write FIFO, providing space is available.
Delayed Transactions, Target I/O Write
Target I/O write operations can be posted (
deltrn
= 1)
or delayed (
deltrn
= 0), and always disconnect burst
accesses into single accesses. For a delayed I/O write,
the Target records the PCI bus command, address, and
first data word (32 or 64 bits) along with its byte
enables (4 or 8 bits) during the initial access. The PCI
bus command and address are put in the Target
address FIFO, and the data word and byte enables are
put in the Target write FIFO. On the PCI bus, the
request is terminated in a retry (with the Master
unaware that the data was snooped), and the FPGA
application is informed that a Target request is pending
via the assertion of
treqn
. The transaction status at this
time is DWR (delayed write request—see PCI Specifi-
cation 2.2: Section 3.3.3.3.6), and subsequent
requests will be terminated in retry until the FPGA
application processes the Target transaction.
相關PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
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