參數(shù)資料
型號(hào): OR3TP12-6BA352
英文描述: Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
中文描述: 用戶可編程ASIC的特殊功能
文件頁數(shù): 36/128頁
文件大?。?/td> 2450K
代理商: OR3TP12-6BA352
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
36
L Lucent Technologies Inc.
PCI Bus Core Master Controller Detailed Description
(continued)
Table 11. Holding Registers, Examples of Typical Operation
Table 12. Master State Counter (MStateCntr) Values and the Corresponding Bus Data
* Same burst length specified in bit 17 of command word for Master reads, or Master write operation.
Address Transfer on Bus
MWData
mwlastcycn
Valid With:
Hold-
ing
Reg.
Select
0
0
1
0
0
0
0
1
1
0
Holding Register 0
Initial Value
Holding Register 1
Initial Value
Master Start
Address
A3
A2
A1
A0
A3
A2
A1
A0
A3
A2
A1
A0
A3
A2
A1
A0
1111
0123
8888
CCCC
1111
4567
5555
9999
DDDD
1111
89AB
3333
6666
AAAA
EEEE
1111
2222
CDEF
4444
7777
BBBB
FFFF
A3
A0
A3
Cmd
A1
A2
A3
Cmd
A3
Cmd
xxxx
1111
1111
1111
1111
1111
1111
8888
8888
8888
xxxx
1111
1111
1111
1111
1111
5555
9999
9999
9999
xxxx
1111
1111
1111
1111
3333
6666
AAAA
AAAA
AAAA
xxxx
1111
2222
2222
2222
4444
7777
BBBB
BBBB
BBBB
xxxx
xxxx
xxxx
0123
0123
0123
0123
0123
0123
CCCC
xxxx
xxxx
xxxx
4567
4567
4567
4567
4567
4567
DDDD
xxxx
xxxx
xxxx
89AB
89AB
89AB
89AB
89AB
89AB
EEEE
xxxx
xxxx
xxxx
CDEF
CDEF
CDEF
CDEF
CDEF
CDEF
FFFF
1111
1111
0123
1111
1111
1111
8888
0123
CCCC
8888
1111
1111
4567
1111
1111
5555
9999
4567
DDDD
9999
1111
1111
89AB
1111
3333
6666
AAAA
89AB
EEEE
AAAA
1111
2222
CDEF
2222
4444
7777
BBBB
CDEF
FFFF
BBBB
MStateCntr[3:0}
Dual-Port Mode (32-Bit Ports)
Quad-Port Mode (16-Bit Ports)
MStateCntr[3:0]
Data on Bus
datafmfpga
BurstLength,
Command Word
Adrs[31:0]
Data on Bus
datatofpga
Read Data [31:0]
Data on Bus
mwdata
Command Word
Data on Bus
mrdata
Read Data [15:0]
0
1
Read Data [63:32]
BurstLength
Adrs[15:0]*
Adrs[15:0]
Adrs[31:16]*
Adrs[31:16]
Adrs[47:32]*
Adrs[47:32]
Adrs[63:48]*
Adrs[63:48]
Write Data [15:0]
Write Data [31:16]
Write Data [47:32]
Write Data [63:48]
Read Data [31:16]
2
Adrs[63:32]
Read Data [47:32]
3
Read Data [63:48]
4
5
6
7
8
9
A
B
Write Data [31:0]
Write Data [63:32]
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
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OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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