參數(shù)資料
型號： OR3TP12-6BA352
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 89/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352
Lucent Technologies Inc.
Lucent Technologies Inc.
89
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
FPGA Configuration Target Controller Data Format
(continued)
Figure 35. Serial Configuration Data Format—Autoincrement Mode
Figure 36. Serial Configuration Data Format—Explicit Mode
Table 26. Configuration Frame Format and Contents
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must be
(n
*
8) + 4, where n s any nonnegative integer and the number of trailing dummy bits must be (n
*
8), where n s any positive integer.
The number of stop bits/frame for slave parallel mode must be (x
*
8), where x is a positive integer. Note also that the bit stream
generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode.
Header
11110010
24-bit Length Count
11111111
0101 1111 1111 1111
Configuration Mode
Reserved [41:0]
ID
Checksum
11111111
01
Data Bits
Preamble.
Configuration frame length.
Trailing header—eight bits.
ID frame header.
00 = autoincrement, 01 = explicit.
Reserved bits set to 0.
20-bit part ID.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header.
Number of data bits depends upon device.
String of 0 bits added to bit stream to make frame header, plus data
bits reach a byte boundary.
8-bit checksum.
Eight stop bits (high) to separate frames.
Address frame header.
14-bit address of location to start data storage.
8-bit checksum.
Eight stop bits (high) to separate frames.
Postamble header.
Dummy address.
16 stop bits.
ID Frame
Configuration
Data
Frame
(repeated for each
data frame)
Alignment Bits = 0
Checksum
11111111
00
14 Address Bits
Checksum
11111111
00
11111111 111111
1111111111111111
Configuration
Address
Frame
Postamble
5-5759(F)
CONFIGURATION DATA
CONFIGURATION DATA
1 0
0 1
0 1
PREAMBLE LENGTH
ID FRAME
CONFIGURATION
DATA FRAME 1
CONFIGURATION
DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER
0 0
0 0
COUNT
5-5760(F)
PREAMBLECOUNT
ID FRAME
CONFIGURATION
DATA FRAME 1
CONFIGURATION
DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER
ADDRESS
FRAME 1
ADDRESS
FRAME 2
0 0
CONFIGURATION DATA
CONFIGURATION DATA
1 0
0 1
0 1
0 0
0 0
0 0
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
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