參數(shù)資料
型號(hào)： OR3TP12-6BA352
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 45/128頁(yè)
文件大小： 2450K
代理商： OR3TP12-6BA352
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Lucent Technologies Inc.
Lucent Technologies Inc.
45
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller
Detailed Description
(continued)
Master Read Byte Enables
During Master reads, read byte enables are always
supplied by the Master to the external Target, even
though on reads the data is flowing in the opposite
direction. Thus, the byte enables cannot be buffered in
the read data FIFO alongside the corresponding data.
Also, the byte enables must be presented on the bus by
the Master at the same time that the data is being pre-
sented on the bus by the external Target (unless the
external Target uses
trdyn
to insert wait-states). The
data provided by the external Target cannot depend on
the byte enables unless wait-states are inserted. Since
the byte enables are not buffered, they are defined in
the Master command word (bits [11:4]) and are held
static throughout the read transaction. Their polarity is
active-low assertion.
For burst read transactions, the read byte enables must
all be asserted. Burst read transactions on a 32-bit
agent (
pci_64bit
= 0) are defined with a burst length of
one or greater, and the read byte enables MRD-
BEN[7:0] asserted. Mixed read byte enables are not
allowed for bursting, but are allowed for single
accesses. Single accesses for a 32-bit PCI bus
(
pci_64bit
= 0) are defined with a read burst length of
one, and the either of the following combination of read
byte enables: MRDBEN[7:4] = 0xf or MRDBEN[3:0] =
0xf. For 64-bit single access (
pci_64bit
= 1, read burst
length = 1), any combination of the read byte enables is
valid.
Wait-States
The Master will only insert wait-states into a read trans-
action when the Master read data FIFO is full, the burst
length count has not been reached, and Target is not
disconnecting. If the FPGA application cannot receive
data from the Master read data FIFOs within an eight
pciclk
period, it is recommended to end the read trans-
action by asserting
mr_stopburstn
and
mrdataen
,
while storing the valid read data word, to avoid exces-
sive wait-state insertion.
Read Transaction Termination
Once initiated, Master read operations will repeat on
the PCI bus until all data is received, an abort occurs
(either Master or Target), the PCI bus’ reset signal
(
rstn
) is asserted, or
mrstopburstn
is asserted. On an
abort, the Master address FIFO is cleared, but the
Master read data FIFO will continue to hold all data
received before the abort. The Master read data FIFO
must be emptied before starting a new Master transac-
tion.
mrstopburstn
can be used by the FPGA application to
terminate a Master read transaction before the read
burst length has been reached. This signal is only
effective if the Master can receive data from an external
Target (
irdynn
and
framen
asserted). Since the FPGA
application has no visibility of the PCI bus control sig-
nals,
mrstopburstn
should be held active until
ma_fulln
is deasserted.
On the Master FIFO interface,
mrlastcycn
indicates
when the last item of the read transaction is being
transferred, although the transaction may have ended
earlier. The transaction on the PCI bus that has been
terminated by Master is indicated by
ma_fulln
being
deasserted.
If a PCI transaction is terminated with a retry or discon-
nect before all data has been received, the PCI bus
core will initiate another Master read operation, con-
tinuing from that point.
Master Read FIFO Interface Reset
The FPGA application can apply a reset signal to place
the Master FIFO interface in a known state, which
clears all FIFOs and resets the
mstatecntr
. The reset
signal,
mfifoclrn
, is asynchronous and therefore
should be asserted for a minimum of one clock cycle
and deasserted for a minimum of one clock cycle
before continuing. It is not recommended to assert
mfifoclrn
while a current PCI transaction is in progress
(
ma_fulln
asserted), since proper PCI bus termination
is not guaranteed. Only
rstn
will reset the internal Mas-
ter PCI state machines, while a PCI transaction is in
progress.
Example: Master Read, Single-Word Transaction
Figure 9 and Figure 10 show the timing of a Master
read, single 32-bit data word, on the dual-port FPGA
interface and quad-port FPGA interface, respectively.
In Figure 9, the command/address phase is initiated by
the FPGA application asserting Master address enable
(
maenn
), while providing the Master command word
and read burst length on bus
datafmfpga
. Assuming
the Master will decode the supplied burst length of one,
32-bit PCI bus width (
pci_64bit
= 0), and read byte
enable (MRDBEN[7:0] = 0xf0), this is a single opera-
tion. On the next clock, the FPGA application provides
the 32-bit address and ends the command/address
phase by asserting
mwlastcycn
.
ma_fulln
then will be
asserted, and the Master will begin negotiating for the
PCI bus.
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