參數(shù)資料
型號(hào)： OR3TP12-6BA352
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 27/128頁
文件大小： 2450K
代理商： OR3TP12-6BA352
Lucent Technologies Inc.
Lucent Technologies Inc.
27
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Symbol
I/O
Description
Clock
Domain
Target Read Data FIFO Signals
(continued)
trpcihold
O
Target Read PCI Bus Hold
. For read transfers to the PCI bus, this signal
delays the start of the data transfer (i.e.,
trdyn
assertion). The data transfer
will begin when
trpcihold
is deasserted or the Target read data FIFO
becomes full. Once asserted, this signal needs to remain asserted for a min-
imum of two
pciclk
cycles.
Target Read Burst Control.
This active-low signal directs the Target to
insert up to eight wait-states between subsequent read data phases before
disconnect. When deasserted, the Target will disconnect immediately when
the Target read data FIFO becomes empty. If
deltrn
is inactive,
trburst-
pendn
must be driven active. Once asserted, this signal needs to remain
asserted for a minimum of two
pciclk
cycles.
pciclk
trburstpendn
O
pciclk
Miscellaneous Signals
pci_intan
O
PCI Interrupt Request
. This active-low signal is used to generate a PCI bus
interrupt and is forwarded by the embedded core as
intan
onto the PCI bus.
Once asserted, this signal needs to remain asserted for a minimum of two
pciclk
cycles.
FPGA Clock 1 and 2
. Clocks used by the Master and Target FIFO interface
logic.
fclk1
and
fclk2
need to be activated for use by the Master and Target
in the FPSC configuration manager. In dual-port mode, only one of these
clocks may be active, while the other should be tied low.
PCI Clock
.
pciclk
is a buffered version of
clk
for use by the FPGA applica-
tion as the main clock, or for control signals which are in the
pciclk
domain
(such as
t_retryn
,
mr_stopburstn
, etc.). The FPGA may route
pciclk
to any
of the FPGA resources,
fclk1
or
fclk2
, programmable clock managers, etc.
PCI Reset
. This active-low signal indicates that a PCI bus reset was received
from the PCI bus (
rstn
).
System Error
. This pin is used by the FPGA to generate a system error on
the PCI bus. This is passed to the PCI bus as
serrn
. Once asserted, this sig-
nal needs to remain asserted for a minimum of two
pciclk
cycles.
—
fclk1
fclk2
O
O
—
pciclk
I
—
pci_rstn
I
—
fpga_syserror
O
pciclk
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
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