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參數(shù)資料
| 型號： | OR3TP12-6BA352 |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 8/128頁 |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA352 |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
8
L Lucent Technologies Inc.
Description
(continued)
FPSC Design Kit
Development is facilitated by an FPSC Design Kit
which, together with ORCA Foundry and third-party
synthesis and simulation engines, provides all software
and documentation required to design and verify an
FPSC implementation. Included in the kit are the FPSC
configuration manager, Verilog and VHDL* simulation
models, all necessary synthesis libraries, and complete
online documentation. The kit's software couples with
ORCA Foundry under the control of the ORCA Foundry
Control Center (OFCC), providing a seamless FPSC
design environment. More information can be obtained
by visiting the ORCAwebsite or contacting a local
sales office, both listed on the last page of this docu-
ment.
ORCA
Foundry
Development System
The ORCAFoundry Development System is used to
process a design from a netlist to a configured FPSC.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry’s timing-driven tools. The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPSC. In the design flow, the
user defines the functionality of the FPGA portion of
the FPSC and embedded core settings at design entry
stage. The embedded core options determine the
FPSC functionality.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPSC. A static timing analysis tool is provided to deter-
mine design speed, and a back-annotated netlist can
be created to allow simulation. Simulation output files
from ORCAFoundry are also compatible with many
third-party analysis tools. Its bit stream generator is
then used to generate the configuration data which is
loaded into the FPSC’s internal configuration RAM.
When using the FPSC configuration manager, the user
selects options that affect the functionality of the FPSC.
Combined with the front-end tools, ORCA Foundry pro-
duces configuration data that implements the various
logic and routing options discussed in this data sheet.
FPGA Logic Overview
ORCASeries 3 FPGA logic is a new generation of
SRAM-based FPGA logic built on the successful
Series 2 FPGA line from Lucent Technologies Micro-
electronics Group, with enhancements and innovations
geared toward today’s high-speed designs and tomor-
row’s systems on a single chip. Designed from the start
to be synthesis friendly and to reduce place and route
times while maintaining the complete routability of the
ORCA Series 2 devices, the Series 3 more than dou-
bles the logic available in each logic block and incorpo-
rates system-level features that can further reduce
logic requirements and increase system speed. ORCA
Series 3 devices contain many new patented enhance-
ments and are offered in a variety of packages, speed
grades, and temperature ranges.
ORCA Series 3 FPGA logic consists of three basic ele-
ments: PLCs, programmable input/output cells (PICs),
and system-level features. An array of PLCs is sur-
rounded by PICs. Each PLC contains a PFU, a SLIC,
local routing resources, and configuration RAM. Most
of the FPGA logic is performed in the PFU, but decod-
ers, PAL-like functions, and 3-state buffering can be
performed in the SLIC. The PICs provide device inputs
and outputs and can be used to register signals and to
perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (
MPI
) and the
PCM
.
* Verilogand VHDLare registered trademarks of Cadance Design
Systems, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
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