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| 型號(hào)： | OR3TP12-6BA352 |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁(yè)數(shù)： | 87/128頁(yè) |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA352 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
87
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed
Description
(continued)
For example, the configuration header and ID frame
from an OR3TP12 bit stream file are as follows:
I
>11111111111100100000010011011000101100001
1111111
I
>01011111111111110000000000000000000000000
000000000000000000000001110000000
I
>0100000101000011111111
This is broken into 32-bit words from left to right, with
the left-most bit the MSB
I
>11111111111100100000010011011000 = >
FFF204D8
I
>10110000111111110101111111111111 = >
C0FF5FFF
Therefore, the first two 32-bit writes into FCDR (0x44)
by PCI configuration writes would be 0xFFF204D8 and
0xC0FF5FF.
9. Read the FCCSR (0x40) until SREMPTY (bit 4)
goes active-high, indicating that the word it con-
tained has been transferred to the FPGA configura-
tion logic.
10. Read the FCCSR (0x40) register and verify no
errors have occurred. (BIT_ERR = 0 (bit 9),
BIT_ERR = 0 (bit 10), and HANDSHAKE_ERROR
= 0 (bit 3), and INITN = 1 (bit 2).
11. Repeat steps 8, 9, and 10 until all the configuration
data has been written.
12. Read the FCCSR (x40) and verify that DONE (bit 1)
went active-high, indicating that the configuration
was successful.
Readback via PCI Interface
The procedure for performing a readback via the PCI
interface is similar to the above procedure for configu-
ration. It is also similar to the standard readback proce-
dure of Series 3 FPGA, where the design needs the
readback controller present in the design, the appropri-
ate bit stream options enabled, and the OR3TP12 con-
figured.
The steps are outlined as follows:
1. Read the FCCSR (0x40) until ASBMODE (bit 0)
goes active-high, indicating that the JTAG controller
is not in control of the FPGA configuration logic.
2. Write to the FCCSR (0x40) with RdCfgN (bit 13)
active-low, enabling the readback mode.
3. Read the FCCSR (0x40) until SRegFull (bit 5) goes
active-high, indicating that a 32-bit word of readback
data is available in register FCDR (0x44).
4. Read the data from the FCDR (0x44) through a con-
figuration read.
5. Repeat steps 3 and 4 until all readback data has
been accessed.
For multiple readbacks, reset the readback mechanism
as follows:
1. Reset RDCFGN (bit 13) in the FCCSR (0x40).
2. Set ConfigFPGA (bit 14) in the FCCSR (0x40).
3. Write the 32-bit word (0xffff_ffff) to the FCDR (0x44).
4. Reset ConfigFPGA (bit 14) in the FCCSR (0x40).
5. Perform readback as described above.
Interaction Among 3TP12 Configuration Modes
The basic FPGA configuration options, including con-
figuration via the microprocessor and boundary-scan
interfaces, are performed in a manner identical to that
of ORCA Series 3 FPGAs. FPSC configuration via the
PCI interface is available at any time, either prior to or
after the FPSC has been configured and regardless of
the value to which the FPGA configuration mode pins
(M2, M1, and M0) have been strapped.
In this priority scheme, a PCI directed configuration will
override any strapped configuration operation already
underway, an FPGA configuration via the boundary-
scan interface will override one via the PCI interface,
and the PRGM pin overrides both.
Once a configuration via the PCI interface is executed,
all options except boundry scan are disabled. To
enable the default mode specified by the mode pins,
assert the RESET pin low after toggling the PRGRM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
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