參數(shù)資料
型號： M68LC302CPU16VCT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 96/128頁
文件大小： 641K
代理商： M68LC302CPU16VCT
Table of Contents
Paragraph
Title
Page
Number
viii
MC68EN302 USER’S MANUAL
MOTOROLA
3.6.2
Read and Write Cycle Operation ............................................................ 3-4
3.7
Refresh Operation................................................................................... 3-5
3.8
DRAM Controller I/O ............................................................................... 3-6
3.8.1
Control Signal Pins ................................................................................. 3-6
3.8.2
Column Address Strobes (CAS1–CAS0)................................................ 3-6
3.8.3
Row Address Strobes (RAS1–RAS0) ..................................................... 3-6
3.8.4
DRAM Read/Write (DRAMRW) .............................................................. 3-6
3.8.5
Address Mux (AMUX) ............................................................................. 3-7
3.8.6
Parity (PARITY1–PARITY0) ................................................................... 3-7
3.8.7
Muxing Scheme ...................................................................................... 3-7
Section 4
ETHERNET Controller
4.1
Register Description.................................................................................4-2
4.1.1
Ethernet Control Register (ECNTRL).......................................................4-3
4.1.2
Ethernet DMA Configuration Status Register (EDMA).............................4-3
4.1.3
Ethernet Maximum Receive Buffer Length (EMRBLR)............................4-5
4.1.4
Interrupt Vector Register (IVEC) ..............................................................4-6
4.1.5
Interrupt Event Register (INTR_EVENT) .................................................4-6
4.1.6
Interrupt Mask Register (INTR_MASK)....................................................4-8
4.1.7
Ethernet Configuration (ECNFIG) ............................................................4-9
4.1.8
Ethernet Test (ETHER_TEST)...............................................................4-10
4.1.9
AR Control Register (AR_CNTRL).........................................................4-11
4.2
Ethernet Buffer Descriptors....................................................................4-12
4.2.1
Ethernet Receive Buffer Descriptor (Rx BD)..........................................4-13
4.2.2
Ethernet Transmit Buffer Descriptor ......................................................4-16
4.3
DMA and Buffer Descriptor Logic ..........................................................4-18
4.3.1
Buffer Descriptor Logic ..........................................................................4-18
4.3.2
DMA Logic .............................................................................................4-19
4.4
Transmit and Receive FIFOs .................................................................4-19
4.4.1
Transmit FIFO........................................................................................4-19
4.4.2
Receive FIFO.........................................................................................4-20
4.5
Ethernet Protocol Logic..........................................................................4-20
4.5.1
Ethernet Transmit ..................................................................................4-20
4.5.2
Ethernet Receive ...................................................................................4-21
4.5.3
Ethernet Loopback.................................................................................4-22
4.6
Ethernet AR (Address Recognition).......................................................4-22
4.6.1
Buffer Descriptor Modification................................................................4-23
4.6.2
Writing Addresses into Tables ...............................................................4-25
4.6.3
Reading Addresses from Tables............................................................4-27
Section 5
Signal Descriptions
5.1
Pin/Signal Combinations..........................................................................5-1
5.2
MC68EN302/MC68302 Common Signals ...............................................5-4
5.3
MC68302 Signals Removed or Redefined...............................................5-5
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