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參數(shù)資料
| 型號(hào)： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 46/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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MC68EN302 Module Bus Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
2-7
2.8 BUS INTERFACE
The MBC is responsible for determining the source of the bus mastership (module bus,
external 68K bus or internal 302 core) and for controlling the direction of the buses. The
layer of buffering between the internal 302 and internal 68000 buses mimics the operation
of the 68302 external bus, giving the module bus the appearance of an external master from
the viewpoint of the internal 302 core. The MBC does not affect the operation of the bus
outside the MC68EN302 unless it arbitrates for that bus and is given bus mastership. The
operation of the MBC as bus master is such that the bus external to the MC68EN302
operates as if an existing 302 peripheral is bus master. This is accomplished by:
Providing I/O control at the pad which overrides the existing 68302 I/O control.
Intercepting the external arbitration signals and merging them with the MBC arbitration.
2.8.1 Bus Arbitration
The MBC provides the circuitry which prioritizes the bus mastership requests in the following
order (highest priority to lowest):
External bus requests
Module bus requests (Ethernet module)
internal 302 core
2.9 DYNAMIC BUS SIZING
The MBC accommodates dynamic bus sizing by providing control to operate on the internal
68000 bus as a 16-bit device while simultaneously providing an 8-bit option externally.
Control is provided via the EN8 bit in the CSER3–CSER0 registers and via the BUSW pin.
The MBC routes data into the proper byte of the word D15–D8, increments the address, and
runs a second bus cycle.
When reading and writing, the MBC will assure proper operation when performing even byte
accesses, even word accesses, and odd byte accesses. Figure 2-4 shows the read cases,
and Figure 2-5 shows the write cases. The even word access is the only case requiring two
bus cycles. When an internal bus cycles is taking place, both AS and the appropriate chip
select will be in operation (except when FAST CYCLES are used). The address is
incremented only in the case of an even address access. Because of this, the address
increment only involves setting A0 to one.
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