參數(shù)資料
型號： M68LC302CPU16VCT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 42/128頁
文件大?。?/td> 641K
代理商： M68LC302CPU16VCT
MC68EN302 Module Bus Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
2-3
is set, the MBC relinquishes the bus when it detects BCLR, allowing the internal 302 core
priority over the DRAM and Ethernet controllers.
MFC—Module Function Code (MFC2-MC0). These bits determine the function code put out
when the Ethernet DMA machine is active.
BB—Bus Error Byte. This status bit (read-only) is the state of Address 0 upon the last
generated bus error. This information is useful when performing exception processing to
determine the cause of bus errors generated when the 8-bit dynamic bus sizing option is
used with the Chip Selects.
PPE—Parity Pin Enable. This bit, if set, enables parity on the appropriate pins. The parity
signals are muxed on three MC68EN302 configuration pins which are sampled at hard reset
to determine device operation. Once out of reset, the parity function may be enabled by the
PPE bit. See 2.10.4 Parity Pin Enable for more details.
PM—Pin Muxes PM9–PM0. Depending upon the setting of these bits, the MC68EN302 is
able to provide some enhancements over the 68302. Because many of these
enhancements are with existing 68302 pins, the enhancements are provided as
programmable options. Table 2-3 shows the effect of the PM bits. All PM bits are cleared at
hardware reset.
2.5 INTERRUPT EXTENSION REGISTER (IER)
This register replaces the MOD, ET7, ET6, and ET1 bits in the pre-existing 302 GIMR
(Global Interrupt Mode Register) requiring that when writing to the internal 302 core GIMR,
the corresponding bits must be written as a zero.This register is $0x0000 upon hardware
reset.
IMOD—Interrupt Mode. This bit determines if the 3 interrupt inputs are configured as IPL
pins or IRQ pins for the MC68EN302 and replace the MOD bit functionality in the internal
Table 2-3. Pin Muxing Operation
Mux Bit
Bit = 0
Pin Function
Bit = 1
Pin Function
PM0
AMUX
BRG1
PM1
RAS0
BRG2/SDS2/PA7
PM2
RAS1
BRG3/PA12
PM3
CAS0
PB0/IACK7
PM4
CAS1
PB1/IACK6
PM5
DRAM_RW
PB2/IACK1
PM6
A0
TOUT1/PB4
PM7
DREQ/PA13
WEL
PM8
DACK/PA14
WEH
PM9
OE
DONE/PA15
15
14
13
12
11
10
9876543210
IMOD
0
MIL
IET7
IET6
IET1
00000000
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