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參數(shù)資料
| 型號： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 76/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
4-12
MC68EN302 REFERENCE MANUAL
MOTOROLA
PA_REJ—Physical address reject.
0 = Frames with physical addresses are accepted if there is a table match, either
perfect or hash.
1 = Frames with physical addresses are accepted if there is no perfect match. If a
physical address has a hash match but not a perfect match, the frame will be
accepted. This bit has no effect on frames with a multicast address.
PROM—Promiscuous mode.
0 = Frames are accepted only if they meet the hashing, perfect address match, or
MULT1–MULT0 criteria
1 = All frames are accepted regardless of address matching or settings of MULT1–
MULT0.
9–0—Reserved.
Should be written as zero by the host processor. These bits are always read as zero.
4.2 ETHERNET BUFFER DESCRIPTORS
The data for the Ethernet frames must reside in memory external to the MC68EN302 device
and is placed in one or more buffers. Buffer descriptors contain pointers to each buffer and
contain the current state of the buffer. The BDs are located inside the MC68EN302 in the
dual port Buffer Descriptor RAM so that the load on the processor bus is minimized.
Software “produces” buffers by allocating/initializing memory and initializing buffer
descriptors in the BDRAM. Setting the most significant bit (R for transmit and E for receive)
in the most significant word of the buffer descriptor initializes the buffer. MC68EN302 DMA
hardware constantly polls the BDs and processes the buffers after they have been
initialized. Processing in the case of transmit indicates that the data in the buffers has been
read into the MC68EN302 and transmitted out the Ethernet interface. Processing in the case
of receive indicates that data received from the Ethernet interface has been placed into data
buffers pointed to by the receive buffer descriptors. Once DMA is complete and the buffer
descriptor status bits have been written, the most signficant bit of the buffer descriptor is
cleared indicating that the buffer has been processed. Software may either poll the BDs or
may rely on the buffer/frame interrupts to detect when the buffers have been consumed.
The ETHER_EN signal operates as a reset to the BD/DMA logic. When ETHER_EN is
deasserted, the BD pointers are reset to point to the starting transmit and receive BDs. The
buffer descriptors are not initialized by hardware during reset. For proper operation, before
setting the ETHER_EN bit, initialize at least one transmit and receive buffer descriptor by
setting the most significant word of the descriptor to $0000 (this does not result in any
transmit or receive operation, but is considered to be initialization). Because the DMA polls
buffer descriptor memory to determine if the R/E bits in the next available BD are set
whenever ETHER_EN=1, initializing ‘n’ buffers, requires software to initialize n+1 buffer
descriptors, setting the most significant bit of the (n+1)th descriptor to 0.
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