參數(shù)資料
型號： M68LC302CPU16VCT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 57/128頁
文件大小： 641K
代理商： M68LC302CPU16VCT
MC68EN302 DRAM Control Module
MOTOROLA
MC68EN302 REFERENCE MANUAL
3-3
Bits 15–8—Reserved. Should be written to zero by the host processor. These bits are
always read as zero.
R7-R0—Refresh Count Bits. The value stored in these bits is multiplied by 16 system clocks
to determine the refresh period. The divide by 16 scheme provides sufficient range to
address systems operating with standard DRAM at frequencies less than 2 Mhz as well as
systems utilizing low power DRAM running at frequencies greater than 25 Mhz. All zeroes
correspond to 4096 system clocks.
3.5 DRAM BASE ADDRESS REGISTER (DBA1-DBA0)
The base address registers for DRAM are two 16-bit registers which are initialized to zero
at hardware reset. These registers hold both the base address of each bank and mask bits
for determining which address bits initiate bus cycle accesses to the DRAM banks.
A23-A17—Base Address Bits. The Base Address Bits determine where the DRAM bank is
located on 128 kbyte boundaries. These bits are compared with the corresponding
addresses generated by the MC68EN302 to determine if a given bus cycle accesses a
particular DRAM bank. These bits are used in conjunction with the Mask Bits to determine
the size and location of a given DRAM bank.
Bits 8–7—Reserved. Should be written to zero by the host processor. These bits are always
read as zero.
M22-17—Mask Bits. These bits are used in conjunction with the Base Address Bits to
determine the size and location of a given DRAM bank.
0 = The corresponding address bit is ignored.
1 = The address compare logic uses the corresponding address bit when determining
if a bus cycle access occurs within the DRAM bank.
V—Valid Bit. This bit is cleared to 0 at hardware reset.
0 = This DRAM bank is not valid
1 = Data for the corresponding DRAM bank data is valid, and DRAM accesses are
decoded by that bank’s circuitry.
3.6 DRAM CONTROL MODULE OPERATION
3.6.1 Reset Operation
Refresh accesses continue if the Ethernet module is reset and during the Reset Instruction
(soft reset), but not during system (hardware) reset.
15
14
13
12
11
10
9876543210
A23
A22
A21
A20
A19
A18
A17
0
M22
M21
M20
M19
M18
M17
V
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