參數(shù)資料
型號： M68LC302CPU16VCT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 70/128頁
文件大小： 641K
代理商： M68LC302CPU16VCT
ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-7
a bit in INTR_EVENT, a one must be written to that bit position. Writing a zero will not
change the value of the bit. This register is cleared upon a hardware reset.
15–11—Reserved. Should be written to zero by the host processor.
HBERR—Heartbeat Error.
When HBC is set, a Heartbeat was not detected within the Heartbeat window following a
transmission.
BABR—Babbling Receiver Error.
Indicates a frame longer than 1520 bytes was received. According to 802.3, frames should
not exceed 1518 bytes but two bytes of slop is allowed. Receive frames exceeding 1520
bytes in length are truncated to prevent receive buffer overflow.
BABT—Babbling Transmitter Error.
The transmitted frame length has exceeded 1520 bytes. This condition is usually caused by
a frame that is too long being placed into the transmit data buffer(s).
GRA—Graceful Stop Complete.
A graceful stop, initiated by the setting of GTS, is now complete. Once the frame that was
in progress when GTS was set has transmitted, this bit is set. If the start of a second frame
is in the FIFO, GRA will be set after the transmission of the second frame. GRA is also set
after EBERR.
BOD—BackOff Done.
Indicates that the backoff timer has expired. This interrupt is used only for production testing
and should normally be ignored. (Set BODEN = 0)
EBERR—Ethernet Bus Error occurred.
Indicates that a bus error occurred when the Ethernet controller was bus master. The
BDERR bits in the EDMA register indicate which buffer descriptor was being used at the
time of the bus error. Once any frames currently in the transmit FIFO have completed
transmission and their status is written to the appropriate buffer descriptor, the GRA bit is
set. If no frames or only a partial frame is in the transmit FIFO, the GRA bit is set immediately
causing the partial frame to become an underrun truncated with a bad CRC.
TFINT—Transmit Frame Interrupt.
Indicates that a frame has been transmitted and that the last corresponding buffer descriptor
has been updated.
RFINT—Receive Frame Interrupt.
Indicates that a frame has been received and that the last corresponding buffer descriptor
has been updated.
15
14
13
12
11
10
9876543210
00000
HBERR BABR BABT
GRA
BOD EBERR TFINT RFINT
BSY
TXB
RXB
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