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| 型號(hào)： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁(yè)數(shù)： | 50/128頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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MC68EN302 Module Bus Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
2-11
Byte (BB) bit is provided in the MBC register. This bit reflects the state of A0 during the last
bus error caused by an access to a byte peripheral.
2.9.3 Retry Handling
In most cases, an MC68EN302 retry is identical to 302 retry operation. If however, a retry
occurs during the second bus cycle of a word access to an 8-bit port, the retry signal is
passed to the initiating master. This causes both of the cycles to be retried, instead of just
the second cycle.
2.10 PARITY LOGIC
The MC68EN302 provides parity support to generate, check, and report parity and parity
errors.
2.10.1 Parity Generation
The MC68EN302 provides the option of generating and checking parity for the 4 chip selects
and the 2 DRAM banks. In the case of a write, parity is generated with one bit of parity per
byte of data. The parity is output on the parity pins and delayed from other data by the
propagation delay through the parity generator.
2.10.2 Parity Checking
Parity checking is performed on read accesses. If the 8-bit option of the Chip Select logic is
used, parity is checked on only the upper 8-bits. In all other options, parity is checked on
both bytes.
2.10.3 Parity Error Reporting
Parity error reporting is accomplished via three mechanisms.
Parity Error Pin
This pin is asserted when a parity error is detected. Parity error detection does not occur
with enough time to generate a bus error on the affected cycle. The parity error pin may be
used with external circuitry to facilitate parity error handling. This pin is not negated until all
the parity error register bits are cleared.
Parity Error Status Bits
There are 6 PCSR register bits dedicated to providing status on parity errors, corresponding
to the 2 DRAM banks and the 4 Chip Selects. If a parity error is detected, the bit that
corresponds to the module that generated the error is set. These bits are reset to zero and
are cleared by writing a one.
Parity Error Interrupt
The PIE bit in the PCSR register is provided to allow the option of generating a level 5 (or 3)
interrupt in the event that a parity error is generated. If this option is selected, the interrupt
is driven after the error is detected until the Parity Error Status Bits are cleared.
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