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參數(shù)資料
| 型號： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 79/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-15
LG—Rx Frame Length Violation, written by Ethernet controller.
A frame length greater than 1520 (maximum allowed receive frame length) was recognized.
In this situation, note that only the first 1520 bytes are written to the data buffer. This bit is
valid only if the L-bit is set. This frame should be discarded.
NO—Rx Nonoctet Aligned Frame, written by Ethernet controller.
The received frame contained a number of bits which is not a multiple of 8, and the CRC
check that occurred at the preceding byte boundary generated an error. This bit is valid only
if the L-bit is set. If this bit is set, the CR bit will not be set. This frame should be discarded.
SH—Short Frame, written by Ethernet controller.
The MC68EN302 does not support SH and this bit is always cleared. This bit indicates that
a frame length less than the minimum defined for this channel was recognized. This frame
should be discarded.
CR—Rx CRC Error, written by Ethernet controller.
This frame contains a CRC error and is an integral number of octets in length. This bit is
valid only if the L-bit is set. This frame should be discarded.
OV—Overrun, written by Ethernet controller.
A receive FIFO overrun occurred during frame reception. During a FIFO overflow, the status
bits also in this word (M, LG, NO, SH, CR, and CL) lose their normal meaning and are zero.
This bit is valid only if the L-bit is set. This frame should be discarded.
CL—Collision, written by Ethernet controller.
A collision occurred during frame reception and the frame was closed. This bit is set only if
a late collision occurred. This bit is valid only if the L-bit is set. This frame should be
discarded.
Data Length, written by Ethernet controller.
Data length indicates the number of octets written by the Ethernet controller into this BD’s
data buffer. It is written by the Ethernet controller upon the close of this BD.
Reason and ARIndex, written by Ethernet controller.
If INDEX_EN=1 in the AR_CNTRL register, then the Reason and ARIndex fields replace the
most significant byte of the Rx Buffer Pointer. The Reason and ARIndex are available on all
buffer descriptors for a frame when INDEX_EN is set, independent of the condition of the L
and F bits. When INDEX_EN = 0 the Reason and ARIndex fields are not modified by
hardware.
Rx Buffer Pointer, written by user.
The receive buffer pointer always points to the first location of the associated data buffer and
must be a multiple of 2. The data buffer must reside in memory external to the Ethernet
controller. When INDEX_EN=1, the most significant byte of the receive buffer pointer is
replaced by a reason and index field. When INDEX_EN=0, the receive buffer pointer is not
modified. See 4.6.1 Buffer Descriptor Modification for more details.
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