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參數(shù)資料
| 型號： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 35/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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MOTOROLA
MC68EN302 REFERENCE MANUAL
1-1
SECTION 1
INTRODUCTION
The MC68EN302 is a multiprotocol integrated communications controller based on the
MC68302. The original MC68302 provided multiple WAN and ISDN support with three serial
communcations channels, glueless memory control for SRAM and EPROM and various
system integration features. The MC68EN302 builds upon the success of the MC68302 by
adding an Ethernet controller which is completely independent of the three on-board serial
channels as well as a DRAM control and a JTAG interface. No communications related
features of the original 302 are lost when using either the Ethernet controller or the DRAM
controller of the MC68EN302.
The Ethernet controller provides a 16-bit interface and provides complete IEEE 802.3
compatibility. The programming model for the Ethernet controller is based on the standard
MC68302 programming model. Buffer descriptors for the Ethernet controller are compatible
wiith the buffer descriptors used by the MC68360 QUICC Ethernet controller.
The DRAM controller is based upon other 300 family memory controllers with specific
enhancements provided for supporting parity and external bus masters.
The JTAG interface is the standard IEEE1149.1 test interface.
1.1 FEATURE LIST
The following MC68EN302 features are in addition to the MC68302 feature list:
Full complement of existing three SCC’s plus Ethernet channel
Ethernet channel fully compliant with IEEE 802.3 MAC Specification.
— Supports data rates up to 10 Mbps.
— Supports the MC68302 style programming model.
— Bus bandwidth requirements reduced through 128 on-chip buffer descriptors.
— Independant 128 byte transmit and receive FIFO’s.
— 64 entry CAM for Address Recognition.
— Ethernet collision results in retransmission from TX FIFO (no external bus access).
— Runt frames automatically cause RX FIFO to flush internally.
— Interfaces to MC68160 for 10Base-T or AUI Connection.
Dynamic Bus Sizing
Glueless ROM and SRAM interface
DRAM Controller
— Glueless DRAM interface for internal bus master
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