參數(shù)資料
型號： M68LC302CPU16VCT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 82/128頁
文件大?。?/td> 641K
代理商： M68LC302CPU16VCT
ETHERNET Controller
4-18
MC68EN302 REFERENCE MANUAL
MOTOROLA
CSL—Carrier Sense Lost, written by Ethernet controller (only valid if L = 1).
Carrier sense dropped out or was never asserted during a collision free frame transmission.
Data Length, written by user.
Data length is the number of octets the Ethernet controller should transmit from this BD’s
data buffer. It is never modified by the Ethernet controller. The value of this field must be
greater than zero.
Tx Buffer Pointer, written by user.
The transmit buffer pointer containing the address of the associated data buffer, may be
even or odd. The buffer must reside in memory external to the MC68EN302. This value is
never modified by the Ethernet controller.
4.3 DMA AND BUFFER DESCRIPTOR LOGIC
The DMA and buffer descriptor modules transfer data between external memory and the TX/
RX FIFOs.
4.3.1 BUFFER DESCRIPTOR LOGIC
Buffer descriptors are stored in the on-chip dual-port RAM. The RAM is sufficient to store
128 buffer descriptors of 4 sixteen-bit-words. The features of the BD circuitry are as follows:
Flexible Buffer Descriptor allocation between transmit and receive;
Multiple buffers per frame
Transmit buffers may start on any byte boundary, Receive buffers must start on even
byte boundaries.
Maximum Receive Buffer size is user controllable;
The Buffer Descriptor space is divided between transmit and receive in various
configurations depending on the value of BDSIZE in the EDMA register. Table 4-2 shows
the starting and ending addresses (offset from MOBA) in the BD RAM for the four options.
The Maximum Receive Buffer Length field (MRBL) in the EMRBLR register determines the
default length of all receive buffers besides the last buffer of a frame (the last buffer is usually
shorter in length than the preceding buffers).
On the transmit side, the MC68EN302 may have up to two separate frames with open
buffers at a specific point in time. While the first frame completes the transmit process, DMA
Table 4-2. BD RAM Address Ranges
BDSIZE
TRANSMIT BUFFER
DESCRIPTOR RANGE
RECEIVE BUFFER
DESCRIPTOR RANGE
NUMBER OF TRANSMIT
BUFFERS
NUMBER OF RECEIVE
BUFFERS
$00
$C00 - $C3F
$C40 - $FFF
8
120
$01
$C00 - $C7F
$C80 - $FFF
16
112
$10
$C00 - $CFF
$D00 - $FFF
32
96
$11
$C00 - $DFF
$E00 - $FFF
64
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