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參數(shù)資料
| 型號(hào)： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 83/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-19
operaton begins for the second frame as the frame status of the first frame is determined.
Frame status is not available until after the 4 microsecond heartbeat window at the end of
transmission.
When ETHER_EN changes from 0 to 1, the transmit process starts at Buffer Descriptor+
$C00 and the receiver begins processing BDs at offset $C40, $C80, $D00, or $E00
depending on BDSIZE. When GTS (graceful transmit stop) is set, the transmitter halts once
any unfinished transmit frames have completed transmission and the Buffer Descriptors
have been updated. The transmitter then generates a GRA interrupt. When GTS is cleared
(0), the transmitter begins transmission with the next frame in the transmit queue.
4.3.2 DMA LOGIC
The DMA block transfers data between the FIFOs and the data buffers that Buffer
Descriptors point to. The DMA block must arbitrate for access to the module bus. Once the
module bus controller has received a grant for the 68000 bus, a module bus grant is passed
to the DMA controller. The DMA controller alternates between transmit and receive DMA,
passing over either one if there is no outstanding data.
If there is receive data but no available buffer to place the data in, a BSY (BUSY) interrupt
is generated.
Once a data flow direction is chosen between transmit and receive, the DMA machine
continues to read a word or byte until it releases the bus and returns to the idle state. The
DMA machine will release the bus on any of the following conditions:
The burst limit counter is reached.
An end of frame (EOF) has been reached.
The receive FIFO has been emptied.
The transmit FIFO has been filled.
At the end of a buffer.
At the beginning or end of a buffer, a byte access occurs if necessary. Once the DMA
machine releases bus mastership, if additional data must be moved, the DMA machine
generates another bus request.
4.4 TRANSMIT AND RECEIVE FIFOS
The Ethernet controller contains separate 128-byte transmit and receive FIFOs organized
as 64 locations x 18 bits each with 16 bits for data and 2 for tag information. Each FIFO has
independent control logic allowing full duplex operation.
4.4.1 TRANSMIT FIFO
The transmit FIFO control logic provides flow control information to the transmit buffer
descriptor logic. The timing for new transmit DMAs depends upon the WMRK and TSRLY
bits in the EDMA register as well as the number of locations currently available in the FIFO.
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